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| (R) Ethernet System Controller * 83C 795 Data Book TABLE OF CONTENTS 83C795 TABLE OF CONTENTS 1.0. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0. FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.0. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1. DESCRIPTION OF DATA PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2. CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.0. PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1. SPECIAL INPUT-TO-OUTPUT PIN MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.0. ETHERNET SYSTEM CONTROLLER REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1. HOST INTERFACE INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1. CR - Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2. EER - EEROM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.3. IOPL - I/O Pipe Data Location Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.4. IOPH - I/O Pipe Data Location High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.5. HWR - Hardware Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.6. BPR - BIOS Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.7. ICR - Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.8. REV/IOPA - Revision/I/O Pipe Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.9. LAN0 - LAN5 - LAN Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.10. BDID - Board ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.11. CKSM - Checksum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.11. GCR2 - General Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.13. IAR - I/O Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.14. RAR - RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.15. BIO - ROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.16. GCR - General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.17. ERFAL - Early Receive Fail Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.18. ERFAH - Early Receive Fail Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2. LAN CONTROLLER REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1. ALICNT - Alignment Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2. BOUND - Receive Boundary Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.3. CMD - Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.4. COLCNT - Collision Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.5. CRCCNT - CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.6. CURR - Current Frame Buffer Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.7. CURRH - Current Frame Buffer Descriptor Pointer Register High . . . . . . . . . . . . . . . . . 25 5.2.8. CURRL - Current Frame Buffer Descriptor Pointer Register Low . . . . . . . . . . . . . . . . . . 25 iii 83C795 TABLE OF CONTENTS 5.2.9. DCON - Data Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.10. ENH - Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.11. ERWCNT - Early Receive Warning Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.12. GROUP0-GROUP7 - Multicast Filter Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.13. INTMASK - Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.14. INTSTAT - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.15. MANCH - Manchester Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.16. MPCNT - Missed Packet Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.17. NEXT - DMA Controller Next Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.18. RADDH - Receive Burst Starting Address High Register . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.19. RADDL - Receive Burst Starting Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.20. RBEGIN - Receive Buffer Starting Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.21. RCNTH - Receive Byte Count High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.22. RCNTL - Receive Byte Count Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.23. RCON - Receive Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.24. RDOWNH - Buffer Room Remaining High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.25. RDOWNL - Buffer Room Remaining Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.26. REND - Receive Buffer End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.27. RSTART - Receive Start Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.28. RSTAT - Receive Packet Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.29. RSTOP - Receive Stop Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.30. RTABH - Receive Buffer Table Pointer High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.31. RTABL - Receive Buffer Table Pointer Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.32. STA0-STA5 - Station Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.33. TADDH - Transmit Burst Starting Address High Register . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.34. TADDL - Transmit Burst Starting Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.35. TBEGIN - Transmit Buffer Starting Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.36. TCNTH - Transmit Frame Length High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.37. TCNTL - Transmit Frame Length Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.38. TCON - Transmit Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.39. TDOWNH - Transfer Count High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.40. TDOWNL - Transfer Count Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.41. TEND - Transfer Buffer End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.42. TLEVEL - Transmit FIFO Track Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.43. TSTARTH - Transmit Start Page High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.44. TSTARTL - Transmit Start Page Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.45. TSTAT - Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.46. TTABH - Transmit Buffer Pointer High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.47. TTABL - Transmit Buffer Pointer Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 iv TABLE OF CONTENTS 83C795 5.2.48. UBRCV - Ultra Board Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.0. HOST INTERFACE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1. MEMORY CACHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1. Zero Wait State Response to Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.2. Staggered Address Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.3. Operation on Micro-Channel Adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2. I/O-MAPPED PIPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3. ADDRESS DECODERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.1. Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2. I/O Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.2.1. PC-98 Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4. BUS CONTROL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.1. IORDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.2. Zero Wait State Response To Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5. MEMORY BUS STRUCTURE AND CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.1. Memory Bus Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.2. 16-Bit Response To Host Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.6. INTERRUPT REQUEST CONTROL LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.7. EEROM CONTROLLER AND ITS UTILIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.1. Initialization Of 83C795 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.2. Retrieval And Storage Of Host Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.1. EEROM Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.2. EEROM Recall Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.3. Storage Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.8. PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8.1. Auto-Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8.2. Plug And Play States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.8.2.1. Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.2.2. Configuration And Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.3. Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.4. Resource String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.8.5. Configuring As A Boot Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.8.6. Configuring With An I/O-Mapped Pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.8.7. Buffer Memory Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.9. EXTERNAL POWER SUPPLY CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.0. LAN CONTROLLER OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1. DMA CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.1. Assembly and Disassembly Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.2. Memory Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 v 83C795 TABLE OF CONTENTS 7.1.3. LAN Controller Internal Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.4. DMA Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.5. How to Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.6. Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2. FIFOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3. RECEIVER NETWORK INTERFACE (PHY-TO-MAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3.1. AUI Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2. Twisted-Pair Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2.1. Extended Length For Twisted-Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.3. Manchester Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.4. Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.5. Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.6. Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.4. MAC RECEIVER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.1. Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.2. Interface to the MAC Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.3. Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.4. Receive Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.5. CRC Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.4.6. Address Recognition Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.4.7. Received Byte Counter and Early Receive Warning Interrupt. . . . . . . . . . . . . . . . . . . . . 71 7.4.7.1. Early Receive Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.8. Receive Protocol FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.9. Reception Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.9.1. Start of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.9.2. End of Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.10. Receiver Blinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.5. TRANSMITTER NETWORK INTERFACE (MAC-TO-PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.1. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2. Manchester Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.3. AUI Differential Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.4. Collision Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.5. Twisted-Pair Differential Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.6. Link Integrity Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.7. Jabber Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.8. SQE Test (Heartbeat Test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.9. Status Indications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6. TRANSMITTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.1. Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 vi TABLE OF CONTENTS 83C795 7.6.2. Preamble Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.3. Transmit Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.4. CRC Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5. Transmit Protocol FSM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5.1. Interframe Gap and Deference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5.2. Collision Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.6. Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.1. Slot Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.2. Backoff Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.3. Collision Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.4. Heartbeat Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7. Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.1. Transmission Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.2. Transmission Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.3. Transmit Underrun. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.4. Early Transmit Underrun Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.5. Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.6. Extensions Beyond 802.3 10Base5 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.6.7.7 Extended Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.0. BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES . . . . . . . . . . . . . . . . . . . . . . . 80 8.1. TRANSMIT PACKETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.1. Single Packet Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.2. Multiple Packet Transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.2.1. Ownership of Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.1.2.2. Modifying the Transmit Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.2. RECEIVE PACKET BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.1. Ring of Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.1.1. Automatic Ring Wrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.1.2. Ring-Empty Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.2. Linked-List Receiver Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.0. ELECTRICAL SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.1. ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.2. RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3. DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3.1. Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3.2. Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.0. AC OPERATING CHARACTERISTICS AND TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.0. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 vii 83C795 LIST OF FIGURES LIST OF FIGURES FIGURE 1-1. 83C795 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 FIGURE 3-1. 83C790 DATA PATH FLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 FIGURE 4-1. 83C790 PIN OUT DIAGRAM (160 PINS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FIGURE 6-1. MEMORY CACHE ARRANGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIGURE 6-2. OVERLAPPING ADDRESS STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FIGURE 6-3. EXTERNAL CASCADED ADDRESS DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FIGURE 6-4. ADDRESS GENERATION PATH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FIGURE 6-5. INTERRUPT CONTROL LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 6-6. EEROM REGISTER LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FIGURE 6-7. PLUG AND PLAY STATE MACHINE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FIGURE 6-8. PLUG AND PLAY CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 FIGURE 7-1. BASIC DMA CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 FIGURE 7-2. AUI/TWISTED-PAIR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 FIGURE 7-3. SIMPLIFIED TRANSMIT CIRCUITRY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 8-1. MULTIPLE FRAME TRANSMIT BUFFER FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FIGURE 8-2. RECEIVER BUFFER FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 FIGURE 8-3. RING BUFFER STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 FIGURE 8-4. RECEIVER BUFFER RING 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 FIGURE 8-5. RECEIVER BUFFER RING 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 FIGURE 8-6. LINKED-LIST BUFFER FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 FIGURE 10-1. SYSTEM CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 FIGURE 10-2. REGISTER ACCESS TIMING - READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 FIGURE 10-3. REGISTER ACCESS TIMING - WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 FIGURE 10-4. 16-BIT REGISTER ACCESS (I/O PIPE ONLY). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 FIGURE 10-5. HOST MEMORY ACCESS (16-BIT, ZWS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 FIGURE 10-6. HOST MEMORY ACCESS (16-BIT, NO ZWS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 FIGURE 10-7. HOST MEMORY ACCESS (8-BIT, ZWS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 FIGURE 10-8. HOST MEMORY ACCESS (8-BIT, NO ZWS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 FIGURE 10-9. ROM ACCESS (8-BIT ONLY, READ ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 FIGURE 10-10. DMA OR MEMORY CACHE WRITES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 FIGURE 10-11. DMA OR MEMORY CACHE READS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 FIGURE 10-12. EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 FIGURE 10-13. TRANSMIT TIMING - START OF TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . 107 FIGURE 10-14. TRANSMIT TIMING - END OF TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 FIGURE 10-15. TRANSMIT TIMING - END OF TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 FIGURE 10-16. RECEIVE TIMING - START OF PACKET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 viii LIST OF FIGURES 83C795 FIGURE 10-17. RECEIVE TIMING - END OF PACKET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 FIGURE 10-18. COLLISION TIMING - TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 FIGURE 10-19. COLLISION TIMING - AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 FIGURE 10-20. LOOPBACK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 FIGURE 10-21. SQE TEST TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 FIGURE 10-22. LINK TEST PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 FIGURE 10-23. ROM DUMP (TEST MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 FIGURE 11-1. 160-PIN PQFP PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ix 83C795 LIST OF TABLES LIST OF TABLES TABLE 4-1. 83C795 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TABLE 4-2. I/O PIN MAPPING SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 4-3. I/O PIN OUTPUT VALUES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 5-1. HOST INTERFACE REGISTERS SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5-2. LAN CONTROLLER REGISTERS - NORMAL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 5-3. LAN CONTROLLER REGISTERS - LINKED-LIST MODE . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 5-4. REGISTER TERM DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 5-5. BUFFER WINDOW SIZE FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 5-6. ROM WINDOW SIZE FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 5-7. INTERRUPT REQUEST FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TABLE 5-8. PAGE SELECT FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 5-9. SLOT TIME SELECTION FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 5-10. GROUP REGISTER BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 5-11. STATION ADDRESS REGISTER BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TABLE 5-12. LOOPBACK TEST SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 5-13. HOST INTERFACE REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 5-14. LAN CONTROLLER REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 6-1. HOST INTERFACE ADDRESS DECODERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 6-2. JUMPER EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TABLE 6-3. EEROM RECALL OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TABLE 6-4. CONFIG REGISTER/INIT PINS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TABLE 6-5. EEROM LOCATION ALLOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TABLE 6-6. AUTO-CONFIGURATION PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TABLE 6-7. PLUG AND PLAY BIT REMAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TABLE 6-8. PLUG AND PLAY RESOURCE STRING STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TABLE 7-1. DMA BURST LENGTH FIELD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 8-1. TSTAT FIELD VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TABLE 8-2. FORMAT OF TRANSMIT DESCRIPTOR TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 TABLE 8-3. MEANING OF DESCRIPTOR TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TABLE 9-1. INPUT PIN VALUES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TABLE 9-2. OUTPUT PIN VALUES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 TABLE 10-1. LIST OF TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 TABLE 10-2. TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TABLE 10-3. TEST PIN I/O MATCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 TABLE 11-1. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 x GENERAL DESCRIPTION 83C795 1.0 GENERAL DESCRIPTION 2.0 FEATURES T he S MC 83C795 E thernet S ys tem Controller implements the IE E E 802.3 protocol for networks s uch as E thernet, Cheapernet, and 10BaseT. It is a highly integrated device that s hrinks the es sence of a LAN adapter card onto a s ingle piece of s ilicon. It includes the 802.3 Media Access Control (MAC) functions, the Phys ical Layer Interface (PLI) for 10BAS E -T media, and ahos t interface des igned for s imple connection to the I ndus try S tandard Architecture (IS A) PC/AT bus. To create a LAN adapter only the 83C795, a single buffer R AM, an E E R OM chip, and an optional R OM for B IOS or IP L code s torage are required. T ransformers and s upporting analog components complete an adapter des ign. All neces s ary control logic is provided by the 83C795. T he resulting LAN adapter appears to the hos t as a block of I/O regis ters with a block of s hared memory, unles s the I/O pipe is us ed. T he base address for I/O regis ters is programmable as is the base addres s and s ize of the buffer memory. T his device is s imilar to the S MC 83C790 LAN controller with three major differences: * A small memory cache has been added for host accesses to shared memory. * An I/O pipe mode has been added to access the buffer memory. * Auto-configurability logic has been added in order to comply with the new ISA Plug and Play specification. As with the 83C790 chip, there are two basicmodes of operation: normal and ALT E GO. In the normal mode, the LAN controller operates much like the 83C690 LAN Controller with received frames being buffered in a ring of contiguous , fixed-s ize buffers . When the ALT E GO feature is enabled, the device s witches to a very different mode of operation. T he differences are s ummarized here and explained in detail throughout the s pecification: 1. 2. Linked-list style of buffering instead of ring buffers. Different register map for LAN controller, exposing new registers for the linked-list buffering. F igure 1-1 depicts the 83C795's functionality. T he bas ic features of the 83C795 chip are s ummarized here: * Memory caching with time-shared access to buffer RAM. * Compliant with the ISA Plug And Play specification * Software compatible with 83C790 drivers * Direct interface with ISA bus without TTL buffers * I/O-mapped pipe access to buffer RAM * Extended length option for the twisted-pair port * Underrun detection in early receive mode * Staggered address transfers supported * Ring-empty bit supplied to host * Automatic ring-wrapping * PC-98 bus support through addition of a jumper * Buffered 20 MHz clock output available through addition of a jumper * Support for diskless workstations via Initial Program Load ROM * Programmable base address and window size for buffer memory and IPL ROM * Support for paging of buffer memory and IPL ROM * Programmable I/O base address * Programmable bus width of either 8 or 16 bits * Zero wait state operation * Au to ma tic lo a di ng o f h os t in terfa ce configuration and LAN address from external serial EEPROM * Separate address and data busses to memory with no external address latches * 7 programmable interrupt levels * Clock oscillator * Full 802.3 MAC layer protocol implementation with extended features * Support for transmission and reception of frames up to 32K bytes long * Transmit frame start at any location - no word alignment required * Two modes of frame buffering: 83C690 mode and descriptor table mode * Loopback modes - internal and external * Full-duplex DMA capability in loopback mode * Built-in AUI serial interface including drivers and receivers 1 83C795 FEATURES * Built-in 10BASE-T serial interface for Ethernet on Twisted-Pair including drivers and receivers * Manchester Encoder/Decoder with clock recovery circuitry * Multicast addressing using 64-bit hashing algorithm * I/O pin mapping enables rapid board test development * 160-pin PQFP package for surface mounting. FIGURE 1-1. 83C795 BLOCK DIAGRAM 2 FUNCTIONAL DESCRIPTION 83C795 3.0 FUNCTIONAL DESCRIPTION 3.2 CONVENTIONS T he principle s ections of the device are the: * Host interface which mediates host access to internal registers and buffer memory. * LAN Controller which performs 802.3 MAC layer protocol and does supporting DMA transfers to and from local buffer memory. * Serial line interface which supplies drivers and receivers for AUI and TP interfaces and port control logic for the 10BASE-T interface. In addition, it provides Manchester encoding and decoding. 3.1 DESCRIPTION OF DATA PATH F i gure 3-1 i ll us tr ates the data path for a 83C795-bas ed board. All internal byte s wapping is handled by the memory cache. T he data bus drivers are des igned to drive the IS A bus directly. A number of conventions are us ed in this databook. 1. A bit may be described as "low" or "logical 0" when its value is set to 0. A bit is described as "high" or "logical 1" when its value is set to 1. The location of a bit is frequently described in this manner: 2. 3 83C795 FUNCTIONAL DESCRIPTION FIGURE 3-1. 83C790 DATA PATH FLOW 4 GENERAL DESCRIPTION 83C795 1.0 GENERAL DESCRIPTION 2.0 FEATURES T he S MC 83C795 E thernet S ys tem Controller implements the IE E E 802.3 protocol for networks s uch as E thernet, Cheapernet, and 10BaseT. It is a highly integrated device that s hrinks the es sence of a LAN adapter card onto a s ingle piece of s ilicon. It includes the 802.3 Media Access Control (MAC) functions, the Phys ical Layer Interface (PLI) for 10BAS E -T media, and ahos t interface des igned for s imple connection to the I ndus try S tandard Architecture (IS A) PC/AT bus. To create a LAN adapter only the 83C795, a single buffer R AM, an E E R OM chip, and an optional R OM for B IOS or IP L code s torage are required. T ransformers and s upporting analog components complete an adapter des ign. All neces s ary control logic is provided by the 83C795. T he resulting LAN adapter appears to the hos t as a block of I/O regis ters with a block of s hared memory, unles s the I/O pipe is us ed. T he base address for I/O regis ters is programmable as is the base addres s and s ize of the buffer memory. T his device is s imilar to the S MC 83C790 LAN controller with three major differences: * A small memory cache has been added for host accesses to shared memory. * An I/O pipe mode has been added to access the buffer memory. * Auto-configurability logic has been added in order to comply with the new ISA Plug and Play specification. As with the 83C790 chip, there are two basicmodes of operation: normal and ALT E GO. In the normal mode, the LAN controller operates much like the 83C690 LAN Controller with received frames being buffered in a ring of contiguous , fixed-s ize buffers . When the ALT E GO feature is enabled, the device s witches to a very different mode of operation. T he differences are s ummarized here and explained in detail throughout the s pecification: 1. 2. Linked-list style of buffering instead of ring buffers. Different register map for LAN controller, exposing new registers for the linked-list buffering. F igure 1-1 depicts the 83C795's functionality. T he bas ic features of the 83C795 chip are s ummarized here: * Memory caching with time-shared access to buffer RAM. * Compliant with the ISA Plug And Play specification * Software compatible with 83C790 drivers * Direct interface with ISA bus without TTL buffers * I/O-mapped pipe access to buffer RAM * Extended length option for the twisted-pair port * Underrun detection in early receive mode * Staggered address transfers supported * Ring-empty bit supplied to host * Automatic ring-wrapping * PC-98 bus support through addition of a jumper * Buffered 20 MHz clock output available through addition of a jumper * Support for diskless workstations via Initial Program Load ROM * Programmable base address and window size for buffer memory and IPL ROM * Support for paging of buffer memory and IPL ROM * Programmable I/O base address * Programmable bus width of either 8 or 16 bits * Zero wait state operation * Au to ma tic lo a di ng o f h os t in terfa ce configuration and LAN address from external serial EEPROM * Separate address and data busses to memory with no external address latches * 7 programmable interrupt levels * Clock oscillator * Full 802.3 MAC layer protocol implementation with extended features * Support for transmission and reception of frames up to 32K bytes long * Transmit frame start at any location - no word alignment required * Two modes of frame buffering: 83C690 mode and descriptor table mode * Loopback modes - internal and external * Full-duplex DMA capability in loopback mode * Built-in AUI serial interface including drivers and receivers 1 83C795 FEATURES * Built-in 10BASE-T serial interface for Ethernet on Twisted-Pair including drivers and receivers * Manchester Encoder/Decoder with clock recovery circuitry * Multicast addressing using 64-bit hashing algorithm * I/O pin mapping enables rapid board test development * 160-pin PQFP package for surface mounting. FIGURE 1-1. 83C795 BLOCK DIAGRAM 2 FUNCTIONAL DESCRIPTION 83C795 3.0 FUNCTIONAL DESCRIPTION 3.2 CONVENTIONS T he principle s ections of the device are the: * Host interface which mediates host access to internal registers and buffer memory. * LAN Controller which performs 802.3 MAC layer protocol and does supporting DMA transfers to and from local buffer memory. * Serial line interface which supplies drivers and receivers for AUI and TP interfaces and port control logic for the 10BASE-T interface. In addition, it provides Manchester encoding and decoding. 3.1 DESCRIPTION OF DATA PATH F i gure 3-1 i ll us tr ates the data path for a 83C795-bas ed board. All internal byte s wapping is handled by the memory cache. T he data bus drivers are des igned to drive the IS A bus directly. A number of conventions are us ed in this databook. 1. A bit may be described as "low" or "logical 0" when its value is set to 0. A bit is described as "high" or "logical 1" when its value is set to 1. The location of a bit is frequently described in this manner: 2. 3 83C795 FUNCTIONAL DESCRIPTION FIGURE 3-1. 83C790 DATA PATH FLOW 4 PIN LIST 83C795 4.0 PIN LIST This section provides the pin list and pin/signal descriptions for the 83C795. Section 4.1 describes the input-to-output pin mapping feature. FIGURE 4-1. 83C790 PIN OUT DIAGRAM (160 PINS) 5 83C795 PIN LIST Mnemonic AE N Pin Number I/O 93 I Description PC ADDR E S S E NABLE . Active low. When Addres s E nable is active the 83C795 responds to any host s trobe (IOR , IOW, ME MR , ME MW, S ME MR , S ME MW). PC ADDR E S S LAT CH E NABLE . Us ed to latch valid address es from the LA bus . Pas s es LA s ignals through internal latches while high and latches them on falling edge. BIAS R E S IS T OR . A resistor from BS R to VDD s ets the internal bias levels . Nominal value is 10K. PLL F ILT E R CAP. A capacitor (nominal value .01F) from CAP to ground is us ed as part of the filter for the internal phas e lock loop. AUI COLLIS ION. CD+ / CD- are us ed by the external trans ceiver to s ignal a collis ion by s ending a 10MHz s ignal. E E R OM Chip S elect. An external 9356 serial E E R OM is used to store up to 2048 bits of configuration data. T hese s ignals (along with LLE D and R LE D) interface with that chip. E E R OM DATA OUT PUT. GE NE R AL PUR POS E OUT PUT. In s ome sys tems , this bit is wired to a s hutdown control input of the DC/DC is olated power supply us ed in 10Bas e2 applications . In other s ys tems , this s upplies a control s ignal for s witching power s upplies . (T he DC s ignal's polarity on the 83C795 is the oppos ite of the 83C790.) Pers onal Computer BUS CLOCK. 16 BIT I/O S E LE CT E D. Active low. Indicates to the PC/AT bus that the I/O response will be 16 bits wide. Only us ed for the I/O pipe. PC I/O R E AD. Active low. R eads an I/O register onto the PC data bus . I/O IOR DY. R es pons e to host acces s which can be us ed directly as 'I/O Channel R eady' when res ponding to a pers onal computer bus . It is pulled low (not ready) to lengthen I/O or memory cycles. When the 83C795 is ready to res pond, the s ignal is driven high until the host acces s is completed, then becomes tris tated. T his signal is driven by a tri-s tate buffer capable of s inking 24 mA. PC I/O WR IT E . Active low. Writes an I/O regis ter from the PC data bus . PC INT E R R UPT R E QUE S T LINE S . Active high. T ristated when not active. IR Q2-9 on the PC/AT bus . IR Q1 is the s ame as the XT XD pin in s ome test modes . IR Q3 on PC/AT bus . S ame as XLOOP in s ome test modes . IR Q5 on PC/AT bus . S ame as XCR S in some tes t modes . IR Q7 on PC/AT bus . S ame as XR XC in some tes t modes . IR Q10 on PC/AT bus . S ame as XR XD in s ome tes t modes . IR Q11 on PC/AT bus . S ame as XCOL in s ome tes t modes. IR Q15 on PC/AT bus . S ame as XT XC in s ome tes t modes. BALE 29 I BS R CAP CD+ CDE E CS 115 113 126 125 132 I I I O E E DO GPOUT 137 110 I/O O HOS T CLK IO16CS IOR IOR DY 71 28 72 90 I/O O I/O O IOW IR Q1 73 108 I/O I/O IR Q2 IR Q3 IR Q4 IR Q5 IR Q6 IR Q7 95 106 107 25 24 23 I/O I/O I/O I/O I/O I/O TABLE 4-1. 83C795 PIN ASSIGNMENTS 6 PIN LIST 83C795 Mnemonic LA17-LA23 Pin Number I/O 13-19 I/O Description PC LA ADDR E S S BUS . Advanced timing vers ion of s ys tem addres s lines A23-A17 from PC/AT bus . T hese are not as s umed to be s table during the entire hos t cycle and are latched internally by the BALE signal (falling edge). T hese s ignals are active high. T WPR LINK S TAT US . If valid data or Link Tes t puls es are received on T PR + / T PR -, LLE D is low (link s tatus OK). When no data or Link Tes t puls es are received, LLE D is high. T he LLE D pin can sink 4mA to drive an external LE D. T his pin als o functions as the E E R OM clock pin (formerly E E S K) and functions as the s hift control pin (formerly S HIF T IN) in scan mode. ME MOR Y 16 S E LE CT E D. Active low. Indicates to the PC/AT bus that R AM acces s res pons e is 16 bits wide. ME MOR Y ADDR E S S LINE S . T hese pins bring out the DMA addres s to memory or feed-through the hos t addres s as modified for paging. When dumping R OM contents , thes e pins pres ent R OM data bits : MA15 R OM30 then R OM31 MA14 R OM28 then R OM29 ... MA00 R OM00 then R OM01 S ame as other MA lines except that during R E S E T, the drivers are disabled and the INIT jumpers are read through thes e pins and latched at the trailing edge of R E S E T. T hey are active high and are pulled up weakly by internal res is tors (35k -150k). To s et a zero value on thes e pins , us e an external pull-down res is tor of 3.6K. LLE D 131 I/O M16CS 26 O O MA15-MA10 139-144 MA09/JMP9 MA08/JMP8 MA07/JMP7 MA06/JMP6 MA05/JMP5 MA04/JMP4 MA03/JMP3 MA02/JMP2 MA01/JMP1 MA00/JMP0 MD7 MD6-MD0 ME MR ME MW OS R R AMOE R AMWR RES ET 145 146 148 149 150 151 152 153 154 155 158 3-9 12 10 112 156 157 95 I/O I/O I/O I/O I O O I/O ME MOR Y DAT A LINE S . T hese pins connect to the data pins of the buffer R AM and the IPL or boot R OM. PC ME MOR Y R E AD for addres s es exceeding 1 M. Active low. PC ME MOR Y WR IT E for addres s es exceeding 1 M. Active low. VCO BIAS R E S IS T OR . A res is tor from OS R to VCC bias es the internal VCO current. Nominal value is 24.9K.. R AM OUT PUT E NABLE . Active low. R AM WR IT E E NABLE . Active low. S YS T E M R E S E T. Active high. TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) 7 83C795 PIN LIST Mnemonic R LE D Pin Number I/O 130 I/O Description R E CV LE D DR IVE R . When on, R LE D drives low to turn on an external LE D. If no data is received, R LE D is off. If data is received, R LE D goes active for approximately 50ms longer than the received packet length. T his pin als o s erves as the E E R OM data in pin (E E DI) and is used as the s can data input (formerly S CANIN) in s can mode. BIOS R OM OUT PUT E NABLE . Active low. Chip S elect for R OM BIOS . Us ed for XT XE in s ome test modes . AUI R E CE IVE . T he Manches ter encoded data from the external trans ceiver is received on R X+ / R X-. PC ADDR E S S BUS . Normal timing vers ion of s ystem addres s lines. T hes e s ignals are active high. R OMCS R X+ R XS A19 - 14 S A13 - 11 S A10 - 09 S A08 - 06 S A05 - 00 S BHE S D15 - 14 S D13 - 12 S D11 - 10 S D09 - 08 S D07 S D06 - 04 S D03 - 02 S D01 - 00 S ME MR 138 124 123 88 - 83 78 - 76 44 - 43 38 - 37 35 - 30 20 45 - 46 48 - 49 51 - 52 54 - 55 69 65 - 63 61 - 60 58 - 57 74 O I I/O I I/O PC BUS HIGH E NABLE . Active low. Indicates a trans fer of data on the upper byte of the data bus, S D8 through S D15. S YS T E M DATA BUS . Data input and output to hos t and shared memory. T hes e signals are active high. I/O LOW ME MOR Y R E AD S T R OBE . R eads buffer memory onto the PC data bus . It is active only when the memory addres s is within the first 1Mb of memory space. Active low. LOW ME MOR Y WR IT E S T R OBE . Writes buffer memory from the PC data bus . S ME MW is active only when the memory address is within the firs t 1Mb of memory s pace. Active low. I/O-MAPPING CONTROL PINS. All signal pins on the 83C795 (except for the analog pins) have been divided into two groups, GROUPA and GROUPB. The functionality of these pins is controlled by the two test pins, as follows: TESTA 1 1 0 0 TESTB 1 0 1 0 GROUPA NORMAL 1 0 TRISTATE GROUPB NORMAL 0 1 TRISTATE S ME MW 75 I/O T ES TA T ES T B 117 118 I TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) 8 PIN LIST 83C795 Mnemonic T LE D Pin Number I/O 129 O Description T R ANS MIT LE D DR IVE R . When on, T LE D drives low to turn on an external LE D. When there is no trans mis s ion (T XE inactive), T LE D is off. When data is trans mitted, T LE D goes active for approximately 50ms longer than the trans mitted packet length. T LE D does not go active for Link Tes t puls es. T his pin also s erves as the s can data output (formerly S CANOUT ) in scan mode, or as a 20 MHz buffered clock output if JUMPE R 8 is ins talled. T WPR R E CE IVE . In 10Bas eT operation, Manches ter encodeddata are received via T PR + / T PR -. T hey are connected to the twis ted pair medium through a transformer and filter. T WPR T R ANS MIT. T PX1+ and T PX1- are used for 10Bas eT only. T hey are the high current pos itive and negative output pins . T WPR T R ANS MIT. T PX2+ and T PX2- are used for 10Bas eT only. T hey are the low current pos itive and negative output pins . AUI T R ANS MIT. T X+ and T X- transmit differential, Manches ter encoded data to the trans ceiver. T hes e are current-driving outputs that furnis h E CL level s ignals when connected to required external pullup resistors of 150. +5 VOLT S OUR CE S . S ome are for logic, some power the pin drivers , and others provide power to the analog portions of the circuit. T PR + T PR T PX1+ T PX1T PX2+ T PX2T X+ T X- 128 127 103 102 104 101 99 98 I O O O VDD (14 pins ) 22, 41, 42, 47, 53, 59, 67, 68, 81, 82, 105, 111, 116, 119, 120, 134, 135, 159, 160 1, 2, 11, 21, 27, 39, 40, 50, 56, 62, 66, 70, 79, 80, 89, 92, 94, 100, 114, 121, 122, 133, 136, 147 96 97 I O VS S (24 pins ) GR OUND. S ome are for logic, s ome power the pin drivers, and others provide power to the analog portions of the circuit. X1 X2 CRYS T AL OS CILLAT OR . T he crys tal is attached across thes e two pins . Must be 20.000 MHz 50 ppm. T his clock operates the chip's logic and is divided by 2 internally to become the transmit clock. PC Z E R O WAIT S TAT E . Active low. Z ero Wait S tate s ignal tells the microprocess or that it can complete the pres ent bus cycle without ins erting any additional wait cycles . Z WS is driven by a tri-s tate driver capable of s inking 24 mA. Z WS 91 O TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.) 9 83C795 PIN LIST 4.1 SPECIAL INPUT-TO-OUTPUT PIN MAPPING The 83C795 provides a special pin mapping feature which can be used for testing. The pins are divided into two groups, GROUPA and GROUPB, for the new I/O pin mapping scheme. GROUPA PINS PIN 3 5 7 9 12 14 16 18 20 24 26 29 31 33 35 37 43 45 48 51 54 57 60 63 65 71 73 75 77 83 85 87 MD06 MD04 MD02 MD00 ME MR LA18 LA20 LA22 S BHE IR Q6 M16CS BALE S A01 S A03 S A05 S A06 S A09 S D15 S D13 S D11 S D09 S D00 S D02 S D04 S D06 BS CK IOW S ME MW S A12 S A14 S A16 S A18 NAME 4 6 8 10 13 15 17 19 23 25 28 30 32 34 36 38 44 46 49 52 55 58 61 64 69 72 74 76 78 84 86 88 PIN MD05 MD03 MD01 ME MW LA17 LA19 LA21 LA23 IR Q7 IR Q15 IO16CS S A00 S A02 S A04 S A07 S A08 S A10 S D14 S D12 S D10 S D08 S D01 S D03 S D05 S D07 IOR S ME MR S A11 S A13 S A15 S A17 S A19 GROUPB PINS NAME TABLE 4-2. I/O PIN MAPPING SCHEME 10 PIN LIST 83C795 GROUPA PINS PIN 90 93 106 108 110 130 132 138 140 142 144 146 149 151 153 155 157 IOR DY AE N IR Q3 IR Q1 GPOUT R LE D E E CS R OMCS MA14 MA12 MA10 MA08 MA06 MA04 MA02 MA00 R AMWR NAME 91 95 107 109 129 131 137 139 141 143 145 148 150 152 154 156 158 PIN GROUPB PINS NAM,E Z WS IR Q2 IR Q4 RES ET R XM LLE D E E DO MA15 MA13 MA11 MA09 MA07 MA05 MA03 MA01 R AMOE MD07 TABLE 4-2. I/O PIN MAPPING SCHEME (CONT.) The I/O pin mapping test for this chip requires only two static vectors. The inputs you must set along with the desired output values are listed in Table 4-3. VECTOR PIN DRIVEN HIGH PINS DRIVEN LOW PINS OUTPUTTING 1's PINS OUTPUTTING 0's 1 2 T E S TA, R XP, T PR P, CDP T E S T B, R XM, T PR M, CDM T E S T B, R XM, T PR M, CDM T E S T A, R XP, T PR P, CDP GR OUPA pins GR OUPB pins GR OUPB pins GR OUPA pins TABLE 4-3. I/O PIN OUTPUT VALUES Note This arrangement does not test the 83C795's analog outputs. 11 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.0 ETHERNET SYSTEM CONTROLLER REGISTERS OFFSET 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F SWH = 0 CR EER IOPL IOPH HWR BPR ICR REV/IOPA LAN0 LAN1 LAN2 LAN3 LAN4 LAN5 BDID CKSM SWH = 1 CR EER IOPL IOPH HWR BPR ICR REV/IOPA GCR2 -- IAR RAR BIO GCR ERFAL ERFAH T he regis ter s tructure of the 83C795 is divided into two regis ter groups : the Hos t Interface regis ters and the LAN Controller regis ters . T he following s ections des cribe the contents of each of these regis ters, detail the way they are access ed, and how they are us ed. Tables 5-1 through 5-3 provide a brief overview of these registers . R efer to the R egister S ummary tables at the end of this s ection for a quick reference guide to all relevant regis ter bit values. TABLE 5-1. HOST INTERFACE REGISTERS SUMMARY 12 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 OFFSET 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F PAGE 0 READ CMD INCRL INCRH BOUND TSTAT COLCNT {0} INTSTAT ERWCNT RENH RCNTL RCNTH RSTAT ALICNT CRCCNT MPCNT PAGE 0 WRITE CMD RSTART RSTOP BOUND TSTARTH TCNTL TCNTH INTSTAT ERWCNT RENH void void RCON TCON DCON INTMASK PAGE 1 READ CMD STA0 STA1 STA2 STA3 STA4 STA5 CURR GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 PAGE 1 WRITE CMD STA0 STA1 STA2 STA3 STA4 STA5 CURR GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 PAGE 2 READ CMD RSTART RSTOP TCNTL TSTARTH NEXT TCNTH ENH RADDL RADDH TADDL TADDH RCON TCON DCON INTMASK PAGE 2 WRITE CMD INCRL INCRH void void NEXT void ENH RADDL RADDH TADDL TADDH void void void void PAGE 3 READ CMD TEST RTEST TTEST TEST2 TSTARTL {0} -- -- -- -- -- -- -- -- MANCH PAGE 3 WRITE CMD TEST RTEST TTEST TEST2 TSTARTL void -- -- -- -- -- -- void void MANCH TABLE 5-2. LAN CONTROLLER REGISTERS - NORMAL MODE OFFSET 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F PAGE 0 READ CMD -- -- CURRL TSTAT COLCNT ERWCNT INTSTAT RTABL RTABH TTABL TTABH RSTAT ALICNT CRCCNT MPCNT PAGE 0 WRITE CMD RBEGIN REND CURRL TEND TBEGIN ERWCNT INTSTAT RTABL RTABH TTABL TTABH RCON TCON -- INTMASK PAGE 1 READ CMD STA0 STA1 STA2 STA3 STA4 STA5 CURRH GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 PAGE 1 WRITE CMD STA0 STA1 STA2 STA3 STA4 STA5 CURRH GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 PAGE 2 READ CMD RBEGIN REND TBEGIN TEND -- -- ENH RDOWNL RDOWNH TDOWNL TDOWNH RCON TCON DCON INTMASK PAGE 2 WRITE CMD -- -- void void void void ENH RDOWNL RDOWNH TDOWNL TDOWNH void void void void PAGE 3 READ CMD -- -- -- -- TSTARTL {0} -- -- -- -- -- -- -- -- MANCH PAGE 3 WRITE CMD -- -- -- -- TSTARTL void -- -- -- -- -- -- void void MANCH TABLE 5-3. LAN CONTROLLER REGISTERS - LINKED-LIST MODE 13 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.1 HOST INTERFACE INTERNAL REGISTERS 5.1.1 CR - Control Register R ead/Write Port = 00 T his regis ter has control over buffer memory enabling and s oft res et of the LAN controller. BIT 7 6 5 4 3 2 1 0 RNIC MENB -- CR4 CR3 RP15 RP14 RP13 CR RESET 1 0 0 0 0 0 0 0 T he following s ection des cribes the contents of the Hos t Interface Internal regis ters. T his regis ter s et cons is ts of 24 regis ters arranged in three groups of eight. T hes e three groups are the LAN Address regis ters , the Hardware Configuration regis ters (which write to and read from the E E R OM), and the Hardware Control registers . T he S witch R egis ter bit (HWR .S WH) determines whether the LAN Addres s R egis ters (S WH = 0) or the Hardware Configuration R egisters (S WH = 1) are vis ible at any one time. (S ee HWR - Hardware S upport R egis ter on page 16 for more information on this bit.) T he Hardware Control regis ters (including the CR , E E R , HWR , BPR , ICR , and R E V regis ters) are always visible. B its within regis ters may als o have different functions depending on whether they are read from or written to. T hroughout this s ection, certain terms are used to describe each regis ter and are defined below: Term RESET INIT Definition Value During RESET Time If the INIT3, 2, 1, 0 jumpers = 1001, this value is loaded into the register immediately after RESET TIME. Some of these values are forced by hardware and others are recalled from EEROM. Recall time is on the order of 2 msec. While the initial recall is ongoing, register may have either the RESET or INIT values This value is loaded when a recall is performed other than after a RESET. Bit 7: RNIC, Reset Network Interface Controller S et R NIC to 1 then back to 0 to force a hardware res et to the LAN Controller. Bit 6: MENB, Memory Enable S et ME NB to 1 to enable hos t acces s to s hared memory. Bit 4-3: CR4-CR3, Reserved For Increase In RP Field Bit 2-0: RP15-RP13, RAM Offset A buffer addres s is created by adding the contents of this field to the difference between the buffer base addres s and the addres s s upplied by the S A19-S A00 lines . T his sum is treated as a movable page offs et which is then ins erted into the buffer window. T his offs et value s hould only be us ed when the memory provided is larger than the window s elected. 5.1.2 EER - EEROM Register R ead/Write Port = 01 T his regis ter controls the s tores to and recalls from E E R OM. In addition, four input pins are vis ible through this regis ter. S ome bits have different functions when read than when written. RECALL REGISTER Possible register values are: VALUES 1 = logical 1 0 = logical 0 PIN = value unknown or wired to external pin. EE = value loaded from EEROM. -- = not used. TABLE 5-4. REGISTER TERM DEFINITIONS 14 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 BIT 7 6 5 4 3 2 1 0 EER READ STO RC EA4 UNLOCK JMP3 JMP2 JMP1 JMP0 RESET 0 0 0 0 PIN PIN PIN PIN operation takes place. E A4 = 1 indicates an access to the Plug and Play res ource string. 5.1.3 IOPL - I/O Pipe Data Location Low R ead/Write Port = 02 T his regis ter and IOPH determine the locations data is read from or written to. BIT 7 6 5 4 3 2 1 0 IOPL IOP7 IOP6 IOP5 IOP4 IOP3 IOP2 IOP1 IOP0 RESET 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 EER WRITE STO RC EA4 UNLOCK EA3 EA2 EA1 EA0 RESET 0 0 0 0 0 1 1 0 Bit 7: STO, Store Into Non-Volatile EEROM S et this bit to 1 to s tore the 8 LAN address regis ters into the E E R OM. T he bit automatically res ets when the s tore is complete. T his function will not be performed unles s the s torage circuit has been armed by a s eries of acces s es to the E E R R egister. (S ee S ection 6.5.2.3 for details .) Bit 6: RC, Recall EEROM S et this bit to 1 to recall the 8 LAN addres s regis ters from E E R OM. T he bit will be automatically res et when the recall is complete. Bit 4: UNLOCK, Unlock Store T his bit is used to unlock the E E PR OM for storage operations. (S ee S ection 6.5.2.3 for details.) Bits 3-0: JMP3-JMP0, Initialization Jumpers T hes e bits are wired to the JMP input pins of the chip. T he JMP field value is used by the recall logic to determine which bank of E E R OM to loadthe hos t interface configuration regis ters from. Bits 5, 3-0: EA4-EA0, EEROM Address Field T his field determines which bank of E E R OM the LAN addres s regis ters are s tored into or recalled from. T his field does not change when a recall Bits 7-0: IOP7-0, I/O Pipe Data Location Low When IOPE N (ICR .4) is s et, thes e are the locations that data is read from or written to in the I/O pipe operation. All 8-bit operations mus t take place through IOPL only. 5.1.4 IOPH - I/O Pipe Data Location High R ead/Write Port = 03 T his regis ter and IOPL determine the locations data is read from or written to. BIT 7 6 5 4 3 2 1 0 IOPH IOP15 IOP14 IOP13 IOP12 IOP11 IOP10 IOP9 IOP8 RESET 0 0 0 0 0 0 0 0 Bits 15-8: IOP15-8, I/O Pipe Data Location High When IOPE N (ICR .4) is s et, thes e are the locations that data is read from or written to in the I/O pipe operation. All 8-bit operations mus t take place through the IOPL regis ter. 15 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.1.5 HWR - Hardware Support Register R ead/Write Port = 04 T his regis ter is us ed to control general purpose outputs and to s witch between configuration and LAN Addres s regis ters . BIT 7 6 5 4 3 2 1 0 HWR READ SWH -- ETHR HOST16 -- ISTAT PNPJMP GPOE RESET 0 0 1 0 0 0 JMP6 0 Bit 5: ETHER, MAC Protocol Type When E T HE R = 1, the 802.3 protocol is provided by this device. T he 83C795 s upports only 802.3. Bit 4: HOST16 T his bit reports whether the 83C795 believes it is connected to an 8-bit or 16-bit host. T he chip determines this by looking at the ME MR pin for activity. Where: HOST16 = 0 - 8-bit host HOST16 = 1 - 16-bit host Bit 3: NUKE, Restart T his bit is 'OR 'ed together with the R E S E T pin s ignal to form the internal R E S E T for the chip. S etting this bit has the s ame effect on the 83C795 as cycling power on the hos t machine. T he chip will res et to its initial condition and reload from the E E R OM. T his bit is cleared when the reset becomes effective. T he NUKE res et executes for 256 chip-clock cycles to allow the MA bus to float and the initialization jumpers to achieve their true values. Note Do not try to access this chip during reset. Bit 2: ISTAT, Interrupt Status IS T AT returns to 1 when Network Interface Controller has an interrupt active. Bit 1: PNPJMP, Plug and Play Jumper Installed A read-only bit that returns a 1 if jumper 6 is ins talled. If PNPJMP = 1 and the PNPE N bit (E R FAL.0) is s et, then Plug and Play hardware is enabled. Bit 0: GPOE, GPX Pin Output Enable T he output is enabled when GPOE = 1. BIT 7 6 5 4 3 2 1 0 HWR WRITE SWH -- -- -- NUKE -- -- GPOE RESET 0 0 1 0 0 0 0 0 Bit 7: SWH, Switch Register Set T his bit s elects between the LAN Addres s regis ters andthe BoardConfiguration regis ters in the regis ter map where: SWH = 0 - LAN Address Registers are visible SWH = 1 - Configuration Registers are visible 16 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 5.1.6 BPR - BIOS Page Register 5.1.7 ICR - Interrupt Control Register R ead/Write Port = 05 T his regis ter controls mapping of R OM window to R OM addres s and other mis cellaneous controls. BIT 7 6 5 4 3 2 1 0 M16EN BP15 BP14 BP13 -- -- SOFT1 SOFT0 BPR RESET 0 0 0 0 0 0 0 0 R ead/Write Port = 06 T his regis ter enables and mas ks interrupts . It is not us ed to s elect IR Q lines . T hat function is performed through the GCR R egis ter. BIT 7 6 5 4 3 2 1 0 MCTEST STAG IOPAV IOPEN SINT MASK2 MASK1 EIL ICR RESET 0 0 0 0 0 0 0 0 Bit 7: M16EN, Memory 16-bit Enable S et M16E N to 1 to enable 16-bit memory access by the host. T his s hould be only s et when all interrupts have been disabled. S ee page 17 for details. Bits 6-4: BP15-13, ROM Offset R OM addres s is created by adding the contents of this field to the difference between R OM bas e addres s and the addres s s upplied on the S A19-S A00 lines . T his sum serves as a movable page offs et into the R OM window. It is intended that the offs et be us ed only when the R OM provided is larger than the window s elected. Bits 1-0: SOFT1-SOFT0 T hes e bits are written and read by s oftware. T hey may be us ed as 'claim' bits for allocation of drivers to multiple LAN connections within a common backplane. Bit 7: MCTEST, Memory Cache Test Bit T he memory cache counters are accelerated when MCT E S T =1. Us e this bit only for tes t purposes . Bit 6: STAG, Staggered Address Enable When S T AG = 1, the lowes t bit in the buffer counter is forced to 1 on memory cache mis s es. Bit 5: IOPAV, I/O Pipe Address Visible When IOPAV = 1, it allows the I/O pipe's temporary address register to be read out of the R E V R egister. Bit 4: IOPEN, I/O Pipe Enable When IOPE N = 1, the I/O pipe is enabled. R egular memory acces s es should be dis abled when this bit is s et. Bit 3: SINT, Software Interrupt S et S INT = 1 to create an interrupt under s oftware control. S et to zero to remove interrupt. F or more details , refer to page 52. Bit 2: MASK2, Mask Interrupt Sources S et MAS K2 to 1 to mas k out interrupt from the NIC. Bit 1: MASK1, Not used Bit 0: EIL, Enable Interrupts S et to 1 to enable interrupts from this device. T his enable controls S INT and interrupts from the LAN controller. F or more details , refer to page 52. 17 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.1.8 REV/IOPA - Revision/I/O Pipe Address Register When IOPAV is s et, the contents of the temporary regis ter can be read from this location. BIT IOPA IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0 RESET 0 0 1 0 0 0 1 0 R ead/Write Port = 07 T his regis ter serves two functions : 1. 2. It provides the host with revision information about the chip (CHIP3-0 and REV3-0). It provides a port for loading the I/O pipe address into the buffer counter. For more on this, see Section 6.2. 7 6 5 4 3 2 1 0 T he revis ion information is read-only and will be returned on reads to this location when the IOPAV bit (ICR .5) is zero. T his information is detailed as follows : BIT 7 6 5 4 3 2 1 0 CHIP3 CHIP2 CHIP1 CHIP0 REV3 REV2 REV1 REV0 REV READ RESET 0 1 0 0 0 0 0 0 Bits 7-0: IOPA7-IOPA0, I/O Pipe Address T his regis ter provides the location of the I/O Pipe address . 5.1.9 LAN0 - LAN5 - LAN Address Registers R ead/Write Ports = 08 - 0D S WH = 0 T hes e s ix LAN addres s registers (along with the B DID and CHKS UM regis ters ) recall or s tore general-purpose data from the E E R OM and, during normal use, recall the permanently-as s igned LAN address for the adapter. REG LAN0 LAN1 LAN2 LAN3 LAN4 LAN5 LN LN07-LN00 LN15-LN08 LN23-LN16 LN31-LN24 LN39-LN32 LNMSB, LN46-LN40 RESET 0 0 0 0 0 0 INIT EE EE EE EE EE EE RECALL EE EE EE EE EE EE Bits 7-4: CHIP3-CHIP0, Chip Type Depending on the condition of Jumper 9, this field yields either 0100 or 0010. A value of 0100 indicates to the hos t that this is an 83C795 device; a value of 0010 indicates an 83C790 device. Bits 3-0: REV3-REV0, Revision Number T hese bits initialize to the revision number of this chip. When the I/O pipe is enabled - that is , when IOPE N is s et (ICR .4) - the I/O pipe addres s is loaded into the buffer counter through this regis ter. S ince the buffer counter is 16-bits wide, two cons ecutive writes are required to accomplis h this us ing this method. * The first write, which contains the lower byte of the address, is stored in a temporary register. * The second write, which contains the upper byte of the address, is then transferred, along with the contents of the temporary register, into the buffer counter. Any hos t access to the chip between the first and s econd writes will automatically res et the proces s . Bits 0-7: LN07-LN00 In normal use, thes e are the leas t s ignificant bits of the globally-as signed LAN addres s block. Bits 8-15: LN08-LN15 In normal us e, LN8-LN15 are part of the globally as signed LAN addres s block. Bits 16-23: LN16-LN23 In normal use, LN16-LN23 are part of the globally as signed LAN addres s block. 18 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 Bits 24-31: LN24-LN31 In normal us e, LN24-LN31 is part of the unique LAN address for each adapter (LN47-LN24) and may be as signed at the time of manufacture for the end product. Bits 32-39: LN32-LN39 In normal us e, LN32-LN39 is part of the unique LAN address for each adapter (LN47-LN24) and may be as signed at the time of manufacture for the end product. Bits 40-46: LN40-LN46 LN40-LN46 forms part of the unique LAN address for each adapter (LN47-LN24) and may be assigned at the time of manufacture for the end product. Bit 47: LNMSB LNMS B is the most significant digit of the unique LAN address block which comprises LN24 through LN47. 5.1.10 BDID - Board ID Register R ead Port = OE S WH=0 T his regis ter is s imilar to the LAN regis ters except that it contains an 8-bit code identifying the board type for software purposes . T he adminis tration of this ID byte is beyondthe s cope of this specification. T his regis ter is stored and recalled along with the LAN regis ters. BIT 7 6 5 4 3 2 1 0 BDID BDID7 BDID6 BDID5 BDID4 BDID3 BDID2 BDID1 BDID0 RESET 0 0 0 0 0 0 0 0 INIT EE EE EE EE EE EE EE EE RECALL EE EE EE EE EE EE EE EE recall of the LAN address, the register's integrity should be confirmed by computing (in software) the checksum of the second group of registers. BIT 7 6 5 4 3 2 1 0 CKSM CHK7 CHK6 CHK5 CHK4 CHK3 CHK2 CHK1 CHK0 RESET 1 1 1 1 1 1 1 1 INIT EE EE EE EE EE EE EE EE RECALL EE EE EE EE EE EE EE EE Bits 7-0: CHK7-CHK0, Checksum Register T he 83C795 stores the checks um amount in this regis ter for reference and comparis on with the LAN regis ters' amounts . 5.1.12 GCR2 - General Control Register 2 R ead/Write Ports = 08 S WH=1 T his regis ter is us ed to hold general control information. BIT 7 6 5 4 3 2 1 0 GCR2 -- -- -- -- -- -- -- PNPIOP RESET 0 0 0 0 0 0 0 0 INIT 0 0 0 0 0 0 0 0 5.1.11 CKSM - Checksum Register R ead/Write Port = OF S WH=0 Before storing a LAN address, CKS M should be programmed with an 8-bit checksum which causes the 2's complement sum of all eight second-group register contents to be FFH. T he sum must include this register. T his register is stored and recalled along with the LAN registers. It is recommended that on Bit 0: PNPIOP, PNP and I/O Mapped Pipe T his bit is us edto communicate to the Plug andPlay logic that the adapter uses the I/O-mapped mode. When PNPIOP = 1, the Plug and Play R AM Control regis ters are dis abled and the R OM Control regis ters are moved from 48h-4Ch to 40h-44h. 5.1.13 IAR - I/O Address Register R ead/Write Port = 0A S WH=1 T his regis ter programs the bas e I/O addres s for the chip. 19 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS BIT 7 6 5 4 3 2 1 0 IAR IA15 IA14 IA13 IA8 IA7 IA6 IA5 PNPBOOT RESET 0 0 0 0 1 0 0 0 INIT 0 0 0 0 1 0 0 0 lines are matched agains t the value F. T his field is not s upported by the Plug and Play hardware. Bits 5-4: RAMSZ1-RAMSZ0, Buffer Window Size Field T his encoded field determines the apparent s ize of the buffer R AM. It is decoded in the following manner: SZ1 0 0 1 1 0 1 0 1 SZ0 Window Size 8K Bytes 16K Bytes 32K Bytes 64K Bytes Bits 7-5: IA15-IA13, I/O Address Lines T hes e bits are compared agains t the A15-A13 lines from the host when IOR or IOW are active and AE N is not. To acces s the chip, the lines mus t match. Bits 4-1: IA8-IA5, I/O Address Lines T hes e bits are compared agains t the A8-5 lines from the host when IOR or IOW are active and AE N is not. To acces s the chip, the lines mus t match. Bit 0: PNPBOOT, Plug and Play Boot Bit PNPBOOT = 1 to indicate to the Plug and Play hardware that the adapter is a boot card. T his allows the 83C795 address decoders to be active without waiting for the Plug and Play hardware activate command. 5.1.14 RAR - RAM Address Register R ead/Write Port = OB S WH=1 T his regis ter controls the bas e addres s and window s ize for the buffer R AM. BIT 7 6 5 4 3 2 1 0 RAR HRAM RA17 RAMSZ1 RAMSZ0 RA16 RA15 RA14 RA13 RESET 0 0 0 0 0 1 0 0 INIT 0 0 0 0 0 1 0 0 TABLE 5-5. BUFFER WINDOW SIZE FIELD Bits 6, 3-0: RA17, RA16-RA13, RAM Base Address Field T hes e bits form part of the bas e addres s for the buffer R AM decoder along with the fixed value of '11' for R A19-R A18. When S A19-S A13 has a value between this base addres s and the base plus the window s ize, the reques t for memory is recognized. Once the S A19-S A13 value is no longer in this range, the host ends the acces s . Note The 64K window size is not supported by Plug and Play. 5.1.15 BIO - ROM Control Register R ead/Write Port = 0C S WH = 1 T his regis ter programs the bas e addres s and window s ize for the external R OM. BIT 7 6 5 4 3 2 1 0 BIO FINE16 BA17 BIOSZ1 BIOSZ0 BA16 BA15 BA14 BA13 RESET 0 0 1 1 0 0 0 0 INIT 0 0 1 1 0 0 0 0 RECALL EE EE EE EE EE EE EE EE Bit 7: HRAM, High RAM Address T his bit provides a means of locating the buffer memory above the 1MB DOS limit. When HR AM = 0, the buffer addres s decoder matches LA23-LA20 agains t zero. When HR AM = 1, the LA23-LA20 20 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 Bit 7: FINE16, Fine Decode When F INE 16 = 1, ME M16CS 's res pons e is generated only when the actual R AM window is being address ed. It includes S A16-S A13 in the address decoding proces s . S ee page 51 for more details . Bits 5-4: BIOSZ1-BIOSZ0, ROM Window Size Field T hes e two bits determine the R OM window size and are decoded in this manner: SZ1 0 0 1 1 0 1 0 1 SZ0 ROM Window Size 8K 16K 32K Disabled Bit 7: XLENGTH, Extended Length Bit Enable When XLE NGT H = 1, the extended length option is enabled as s pecified by the 802.3 s pecification (refer to page 69). Bit 5: ZWSEN, Zero Wait State Enable T his bit is s et to 1 to enable the chip to generate a Z WS response when the R AM is acces sed and available to the hos t. Bit 4: RIPL, Software Flag Bits 6, 3-2: IR2-IR0, Interrupt Request Field T hes e bits form an encoded field to s elect through which IR Q pin the interrupt output is channeled. Becaus e of Plug and Play logic, it is neces sary to connect the interrupt pins to s pecific lines on the IS A bus , as s hown below. T he interrupt reques t pins and their corresponding IS A lines are decoded in this fas hion: IRQ2 0 0 0 0 1 1 1 1 IRQ1 0 0 1 1 0 0 1 1 IRQ0 0 1 0 1 0 1 0 1 IRQ Pin Selected None IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ISA Bus Line None IRQ2/9 IRQ3 IRQ5 IRQ7 IRQ10 IRQ11 IRQ15 TABLE 5-6. ROM WINDOW SIZE FIELD Bits 6, 3-0: BA17, BA16-BA13, Base Address Field T hes e bits form part of the bas e addres s for the R OM decoder along with the fixed value of '11' for BA19-BA18. When S A19-S A13 has a value between this base addres s and the bas e plus the window s ize and S ME MR are active, a reques t for the R OM is recognized. A chip s elect will be generated to the R OM if not dis abled. Memory acces s at the s ame addres s is blocked if R OM is enabled. 5.1.16 GCR - General Control Register R ead/Write Port = OD S WH = 1 T his register controls interrupt level s election, zero wait state res pons e, and s everal other functions . BIT 7 6 5 4 3 2 1 0 GCR XLENGTH IR2 ZWSEN RIPL IR1 IR0 GPOUT LIT RESET INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RECALL EE EE EE EE EE EE EE EE TABLE 5-7. INTERRUPT REQUEST FIELD Bit 1: GPOUT, General Purpose Output T his bit controls the GPOUT pin of the chip. When GPOUT = 1, it caus es the GPOUT pin to drive low. In s ome s ys tems , this bit is wired to a s hutdown control input for DC/DC is olated power s upply us ed in 10Bas e2 applications . For more information on this feature, refer to S ection 6.7. Bit 0: LIT, Link Integrity Test T his bit controls the Link Integrity Tes t. In S TAR LAN-10 networks, the Link Integrity Tes t s hould be dis abled. LIT = 0 - Link Test is Disabled LIT = 1 - Link Test is Enabled. 21 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS Dis abling the Link Integrity Tes t (LIT ) forces the 83C795 to s elect the twis ted-pair interface. When LIT is enabled, the twisted-pair interface will be automatically s elected when link activity is found and the AUI interface will be selected when the twisted-pair link enters the 10BAS E -T link fail s tate. 5.1.17 ERFAL - Early Receive Fail Address Low Register R ead/Write Port = OE S WH = 1 T his regis ter contains the lower eight bits for the address at which the early-receive logic detected an underrun. T his register als o contains a control bit for the Plug and Play logic. BIT 7 6 5 4 3 2 1 0 ERFAL ERFA7 ERFA6 ERFA5 ERFA4 ERFA3 ERFA2 -- PNPEN RESET -- -- -- -- -- -- 0 1 RECALL -- -- -- -- -- -- 0 EE 5.1.18 ERFAH - Early Receive Fail Address High Register R ead/Write Port = OF S WH = 1 T his regis ter contains the higher eight bits for the address at which the early receive logic detected an underrun. BIT 7 6 5 4 3 2 1 0 ERFAH ERFA15 ERFA14 ERFA13 ERFA12 ERFA11 ERFA10 ERFA09 ERFA08 RESET -- -- -- -- -- -- -- -- RECALL -- -- -- -- -- -- -- -- Bits 7-0: ERFA15-8, Early Receive Failure Address T his register contains the higher eight bits of the address where the early receive logic detected an underrun. Bits 7-2: ERFA7-2, Early Receive Failure Address T his regis ter contains the lower eight bits of the address where the early receive logic detected an underrun. T he comparis on has a granularity of 4 bytes s o the leas t s ignificant two bits are zero. T his value is read-only. Bit 0: PNPEN, Plug and Play Enable When PNPE N = 1 along with the ins tallation of JUMPE R 6, Plug and Play logic is enabled. T his bit is readable but can only be s et by the initial E E R OM load. 22 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 5.2 LAN CONTROLLER REGISTER DESCRIPTIONS 5.2.1 ALICNT - Alignment Error Counter Register To s implify the programming model for the LAN controller and retain compatibility with the S MC 83C690 LAN Controller, the internal regis ters are dividedinto two addres s maps . T he default address map is us ed for R ing-s tyle buffering (like the 83C690). T hos e regis ters needed for linked-lis t buffering are grouped together in the alternate addres s map and are enabled through the E nhancement (E NH) regis ter des cribed s tarting on page 26. E ach map provides acces s to all regis ters neces s ary for operating that particular buffering mode. Many registers are vis ible in both maps , although not always at the s ame addres s in each. To facilitate manufacturing test of the device, many internal regis ters can be acces sed in one or both of thes e maps . Within each map, the regis ters are organized into 4 pages of 16 regis ters each. Only one page is vis ible at atime. Page s election is made through the Command (CMD) regis ter described s tarting on page 24. T he addres ses lis ted in this s pecification are in an abbreviated form. T he firs t hex digit is really a two-bit 'page' value which is written into the LAN COMMAND (CMD) regis ter to acces s the 16 regis ters visible for that page. T he digits after the colon are the offs et within the 83C795's L AN Controller I/O s egment in this manner: Normal Map R ead Port = 0:1D Link-List Map R ead Port = 0:1D T his register is the alignment error counter. It is incremented by the receive unit when a packet is received with a frame alignment error. Only packets whose addres ses are recognized will be included in this tally. T he counter will increment to 255 and s top if additional alignment errors are detected. T he counter is cleared when read. BIT 7 6 5 4 3 2 1 0 5.2.2 ALICNT CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 RESET 0 0 0 0 0 0 0 0 BOUND - Receive Boundary Page Register Normal Map R ead/Write Port = 0:13 T he R eceive Boundary Page R egis ter points to the oldest us ed receive buffer in the ring. It is us ed to prevent overflow in the buffer ring. T he DMA compares the contents of this register to the next buffer addres s when linking buffers together for s torage of a received frame. If the contents match the next buffer addres s , the DMA operation is aborted. Only A08-A15 are s pecified s ince all buffers are aligned on 256-byte boundaries . F or more information, refer to page 85. BIT 7 6 5 4 3 2 1 0 BOUND A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X page:offset To determine the correct addres s , you mus t firs t know the 83C795's base addres s then s elect the correct page and finally s elect the correct offset. S o, for example, "3:1C" indicates that the addres s for this particular regis ter is found on page 3 at the offs et value 1C. In the following des criptions , the mos t significant bit position is numbered '7'. T he line labelled R E S E T s hows the initial values loaded into the regis ter by as sertion of the R E S E T pin. T he symbol '0' denotes void bits which always return zero when read. 23 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.3 CMD - Command Register Normal Map R ead/Write Port = X:10 Linked-List Map R ead/Write Port = X:10 BIT 7 6 5 4 3 2 1 0 CMD PS1 PS0 RFU ENETCH DISETCH TXP STA STP RESET 0 0 0 0 0 0 0 1 T he 83C795 clears this bit upon completion or abortion of the transmis sion. Bit 1: STA, Start Bit S et the S T A bit to activate the 83C795 after power up or when the 83C795 has been res et by a software command. No frames can be s ent or received until this bit has been s et. T he us er's s oftware s hould s et up the other regis ters prior to bringing the device on line, but setting this bit is the actual command which brings the T rans mit and R eceive portions of the device online. Once set, this bit may be cleared and the 83C795 will continue to remain online. Bit 0: STP, Stop Bit S et the S T P bit to take the chip offline and dis engage from the LAN. Frames partially trans mitted or received are completed before res et occurs. INT S T AT.R S T is set high when the T ransmit and R eceive s ection have completed all outs tanding operations (see page 28). No frames will be received or transmitted until the s tart bit has been s et. 5.2.4 COLCNT - Collision Count Register Normal Map R ead Port = 0:15 Linked-List Map R ead Port = 0:15 T his regis ter contains the number of collis ions detected while attempting to trans mit the current (or mos t recent) packet. It is cleared to zero at the start of trans miss ion. If no collis ions are detected, the counter wil l r ead z er o. F or each collis ion encountered, the count is incremented. If more than 15 collisions occur, the abort bit of T S T AT is set and the count is res et to zero (s ee page 38). BIT 7 6 5 4 3 2 1 0 COLCNT T10 T9 T8 T7 CT3 CT2 CT1 CT0 RESET 0 0 0 0 0 0 0 0 T he Command regis ter is us ed to initialize the 83C795 chip, s tart trans mis s ions , and s witch pages . Bits 7-6: PS1-PS0, Page Select T his 2-bit field des ignates which of 4 pages is s howing. T hey decode as follows: PS1 0 1 0 1 0 0 1 1 PS0 Page Select Page 1 Page 2 Page 3 Page 4 TABLE 5-8. PAGE SELECT FIELD Bit 5: RFU, Reserved for Future Use T his bit is not us ed by 83C795 and always returns zero when read. Bit 4: ENETCH, Enable Early Transmit Checking By setting this bit to 1, it enables comparis on of trans mit DMA addres s agains t the hos t memory write address . Once s et, this bit can be cleared and the 83C795 continues to check trans mis s ion addres s es until DIS E T CH is s et. S ee page 78 for more details . Bit 3: DISETCH, Disable Early Transmit Checking By s etting this bit to 1, it dis ables the early transmit address checking. Once s et, the bit can be cleared and trans mit addres s checking is s uppres s ed until E NE T CH is s et. S ee page 78 for more details. Bit 2: TXP, Transmit packet S et this bit after loading the T rans mit Buffer and Control regis ters to initiate trans mis s ion of apacket. 24 Bits 7-4: T10-T7, Backoff Counter T hes e 4 cons ecutive bits always return zero. ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 Bits 3-0: CT3-CT0, Collision Counter T hes e bits indicate the value of the collis ion counter. T hey are always readable. 5.2.5 CRCCNT - CRC Error Counter Normal Map R ead Port = 0:1E Linked-List Map R ead Port = 0:1E T his regis ter is incremented by the receive unit when a packet is received with a CR C error. Only packets whos e addres s is recognized will be included in this tally. When a 'runt' frame is received with a CR C error, CR CCNT is incremented if R CON.R UNT S is enabled (s ee page 32). T he counter will increment to 255 and s tick if additional CR C errors are detected. T he counter is cleared when read. BIT 7 6 5 4 3 2 1 0 5.2.6 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 CRCCNT RESET 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 5.2.7 CURR A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X CURRH - Current Frame Buffer Descriptor Pointer Register High Linked-List Map R ead/Write Port = 1:17 T his regis ter is one of a pair of registers (CUR R H and CUR R L) that point to the firs t buffer descriptor us ed for s torage of the pres ent frame. T hey are us ed by DMA as a backup addres s for recovering buffers in the cas e of a flawed packet and to facilitate s torage of buffer header information. Neither the CUR R H nor CUR R L regis ters s hould be altered by the user. T hey are acces s ible for tes t purposes only. BIT 7 6 5 4 3 2 1 0 5.2.8 CURRH A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X CURR - Current Frame Buffer Pointer Register Normal Map R ead/Write Port = 1:17 T his regis ter points to the firs t buffer us ed for s torage of the pres ent frame. It is used by DMA as a backup addres s for recovering buffers in cas e of a flawed packet and facilitates s torage of buffer header information. T he CUR R register s hould be initialized to the same value as R S T AR T (s ee page 33) andnot altered thereafter by the user unles s the controller is res et. Only A08-A15 are s pecified s i nce al l buffer s ar e aligned on 256-byte boundaries . CURRL - Current Frame Buffer Descriptor Pointer Register Low Linked-List Map R ead/Write Port = 0:13 T his regis ter is one of a pair of registers (CUR R H and CUR R L) that point to the firs t buffer descriptor us ed for s torage of the pres ent frame. T hey are us ed by DMA as a backup addres s for recovering buffers in the cas e of a flawed packet and to facilitate s torage of buffer header information. Neither the CUR R H nor CUR R L regis ters s hould be altered by the user. T hey are acces s ible for tes t purposes only. 25 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS BIT 7 6 5 4 3 2 1 0 CURRL A07 A06 A05 A04 A03 A02 A01 A00 RESET X X X X X X X X ALTEGO = 1 Des ignates linked-lis t receive buffering and multiple frame trans mis s ion format. T he regis ter addres s map is s elected with this bit, exposing the regis ters as sociated with the s elected buffering mode. Bits 4-3: SLOT1-0, Slot Time Selection T his two-bit field s elects the s lot time according to Table 5-10. SLOT1 0 1 1 SLOT0 X 0 1 Slot Time 512 bit times (Ethernet) 256 bit times 1024 bit times 5.2.9 DCON - Data Configuration Register Linked-List Map R ead Port = 2:1E Linked-Lis t Map Write Port = 0:1E T his regis ter always returns 41h. In the 83C790 this regis ter controlled DMA burs t lengths ; however, the 83C795 is hardwired for 8-byte burs ts . R efer to page 65 for more information. 5.2.10 ENH - Enhancement Register Normal Map R ead/Write Port = 2:17 Linked-List Map R ead/Write Port = 2:17 T his regis ter enables enhancement features . BIT 7 6 5 4 3 2 1 0 ENH -- -- ALTEGO SLOT1 SLOT0 EOTINT -- SBACK RESET 0 1 0 0 0 0 0 0 TABLE 5-9. SLOT TIME SELECTION FIELD Bit 2: EOTINT, Interrupt on End-of-Transmit EOTINT = 1 Interrupt on E nd-of-T rans mit chain ins tead of each trans mittedframe. T his bit is ignoredif not operating in multiple frame trans mis s ion mode. EOTINT = 0 Interrupt on each trans mitted frame. Bit 0: SBACK, Enable Stop Backup Modifications SBACK = 1 E nable the S top Backoff modifications to the backoff timer. SBACK = 0 Normal backoff. 5.2.11 ERWCNT - Early Receive Warning Threshold Register Normal Map R ead/Write Port = 0:18 Linked-List Map R ead/Write Port = 0:18 T his register contains the R eceived Byte Count thres hold at which the E arly R eceive Warning interrupt is generated. T he E R W interrupt is generated when R BC E RW. Bits 3-0 of R BC are ignored. F or more information on this register, refer to page 71. Bits 7-6: Unused Bit 5: ALTEGO, Buffering Format Selection ALTEGO = 0 Des ignates ring buffering and s ingle frame trans miss ion format. T his is es sentially 8390/83C690 compatibility mode. 26 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 BIT 7 6 5 4 3 2 1 0 ERWCNT ERW11 ERW10 ERW9 ERW8 ERW7 ERW6 ERW5 ERW4 RESET 0 0 0 0 0 0 0 0 5.2.13 INTMASK - Interrupt Mask Register Normal Map R ead Port = 2:1F Normal Map Write Port = 0:1F Linked-List Map R ead Port = 2:1F Linked-Lis t Write Port = 0:1F T he Interrupt Mas k R egis ter is us ed to mas k out certain interrupt s ources s electively. Mas k bits s et to '1' allow the corres ponding interrupts to caus e an IR Q. Mas k bits set to '0' block their res pective interrupt s ources . BIT 7 6 5 4 3 2 1 0 INTMASK -- ERWE CNTE OVWE TXEE RXEE PTXE PRXE RESET 0 0 0 0 0 0 0 0 5.2.12 GROUP0-GROUP7 - Multicast Filter Table Registers GROUP Register GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 Normal Map Port Address Read Write 1:18 1:18 1:19 1:19 1:1A 1:1A 1:1B 1:1B 1:1C 1:1C 1:1D 1:1D 1:1E 1:1E 1:1F 1:1F Linked-List Map Port Address Read Write 1:18 1:18 1:19 1:19 1:1A 1:1A 1:1B 1:1B 1:1C 1:1C 1:1D 1:1D 1:1E 1:1E 1:1F 1:1F Bit 6: ERWE, Early Receive Warning Enable When E R WE = 1, this bit enables E arly R eceive Warning as defined by the E R W bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) Bit 5: CNTE, Counter Overflow Enable When CNT E = 1, this bit enables Counter Overflow as defined by the CNT bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) Bit 4: OVWE, Overwrite Warning Enable When OVWE = 1, this bit enables Overwrite Warning as defined by the OVW bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) T hes e 8 registers hold the node's Multicas t filter table. S ee T able 5-10 for the regis ters ' bit as signments . GROUP Registers GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 BIT 7 GA07 GA15 GA23 GA31 GA39 GA47 GA55 GA63 BIT 6 GA06 GA14 GA22 GA30 GA38 GA46 GA54 GA62 BIT 5 GA05 GA13 GA21 GA29 GA37 GA45 GA53 GA61 BIT 4 GA04 GA12 GA20 GA28 GA36 GA44 GA52 GA60 BIT 3 GA03 GA11 GA19 GA27 GA35 GA43 GA51 GA59 BIT 2 GA02 GA10 GA18 GA26 GA34 GA42 GA50 GA58 BIT 1 GA01 GA09 GA17 GA25 GA33 GA41 GA49 GA57 BIT 0 GA00 GA08 GA16 GA24 GA32 GA40 GA48 GA56 TABLE 5-10. GROUP REGISTER BITS 27 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS Bit 3: TXEE, Transmit Error Enable When T XE E = 1, this bit enables T rans mit E rror as defined by the T XE bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) Bit 2: RXEE, Receive Error Enable When R XE E = 1, this bit enables R eceive E rror as defined by the R XE bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) Bit 1: PTXE, Packet Transmitted Enable When T XE E = 1, this bit enables Packet T rans mitted as defined by the PT X bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) Bit 0: PRXE, Packet Received Enable When PR XE = 1, this bit enables Packet R eceived as defined by the PR XE bit in the Interrupt S tatus R egis ter. (S ee the next regis ter, INT S T AT.) 5.2.14 INTSTAT - Interrupt Status Register Normal Map R ead/Write Port = 0:17 Linked-List Map R ead/Write Port = 0:17 T he Interrupt S tatus R egis ter enables the hos t to determine the caus e of an interrupt and to evaluate pending or mas ked interrupts . Mas ked-out interrupts are visible in this regis ter although they will not generate an IR Q to the hos t. Pending interrupts can be cleared by writing '1' to the as sociated bit of this regis ter. T he IR Q s ignal is active as long as any unmas ked interrupt bit remains s et. F or more details , see page 80. BIT 7 6 5 4 3 2 1 0 INTSTAT RST ERW CNT OVW TXE RXE PTX PRX RESET 1 0 0 0 0 0 0 0 Bit 6: ERW, Early Receive Warning When this bit is s et it indicates that the number of bytes received in the current frame has exceeded the programmable limit of the E R WCNT register. Bit 5: CNT, Counter Overflow When this bit is set it indicates that the MS B of one or more network error counters has been set. Bit 4: OVW, Overwrite Warning T his bit is s et when the receive DMA mus t abort frame reception due to a lack of receive buffers . Bit 3: TXE, Transmit Error T his bit is set when exces sive collis ions , out-of-window collisions , F IF O underrun, or early transmit addres s violations prevent trans mis s ion of a packet. Bit 2: RXE, Receive Error T his bit is s et when a packet is received with one or more of the following errors : * CRC error (happens when SEP is enabled) * Frame alignment error (happens when SEP is enabled) * FIFO overrun * Missed packet (monitor mode) T his interrupt will not be pos ted if a DMA Abort occurs, a condition indicated by the as sertion of an OVW interrupt. If R XE is previous ly s et, it will not be changed due to OVW. Bit 1: PTX, Packet Transmitted T his bit is s et when a packet is trans mitteds ucces s fully. When the bit E NH.E OT INT is s et in Multiple Packet T ransmit mode (see page 5-26), setting of this interrupt is deferred until the entire transmit chain has been process ed. PT X is then s et if any packet in the chain was trans mitted s ucces sfully, or if a zero length trans mit chain was proces s ed. Bit 0: PRX, Packet Received When PR X = 1, it indicates that a packet was received with no errors . Bit 7: RST, Reset Status T his bit is s et by 83C795 when its T rans mit and R eceive s ections are s topped in res pons e to the as sertion of the R E S E T pin or the s etting of the CMD.S T P bit. T he R S T bit does not generate an interrupt. 28 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 5.2.15 MANCH - Manchester Management Register Normal Map R ead/Write Port = 3:1F Linked-List Map R ead/Write Port = 3:1F T his regis ter allows the reading back of the 10Bas eT s tatus LE D drivers to support network and s tation management functions . It als o enables and contr ols the 83C795's internal Manches ter encoder/decoder. BIT 7 6 5 4 3 2 1 0 MANDIS SEL 0 ENAPOL PLED LLED RLED TLED MANCH RESET 0 1 0 1 0 0 0 0 Bit 2: LLED, Link Status LED Readback When LLE D = 1, this LE D is on (output s inking current). Bit 1: RLED, Receive LED Readback When R LE D = 1, this LE D is on (output s inking current). Bit 0: TLED, Transmit LED Readback When T LE D = 1, this LE D is on (output s inking current). 5.2.16 MPCNT - Missed Packet Error Counter Register Normal Map R ead Port = 0:1F Linked-List Map R ead Port = 0:1F T his regis ter is incremented by the receive unit whenever it cannot receive a packet due to a lack of receive buffers , receive F IF O overflow, or becaus e the receiver is in monitor mode. Only packets whos e addres s is recognized will be included in this tally. T he counter will increment to 255 and stick if additional packets are mis s ed. T he counter is cleared when read. BIT 7 6 5 4 3 2 1 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 MPCNT RESET 0 0 0 0 0 0 0 0 Bit 7: MANDIS, Manchester Disable MANDIS = 1 - dis ables the internal Manches ter E ncoder/Decoder. When dis abled, the LAN Controller us es the decoder s erial interface cons is ting of thes e lines : XT XD, XT XE , XT XC, XR XD, XR XC, XCR S , XCOL, XLOOP. MANDI S = 0 - E nabl es the Manches ter E ncoder/Decoder. Bit 6: SEL, Select AUI Mode For Idle State S E L = 0 - T X+ is pos itive in relation to T X-. S E L = 1 - T X+ = T X-. Bit 4: ENAPOL, Automatic Polarity Correct E NAPOL = 1 - E nable Auto Polarity Correct E NAPOL = 0 - Dis able Auto Polarity Correct Bit 3: PLED, TPRX Polarity LED Readback When PLE D = 1, this LE D is on. Note There is no P L E Dpin onto which this signal might be driven. 29 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.17 NEXT - DMA Controller Next Buffer Register Normal Map R ead/Write Port = 2:15 T his is a working register of the DMA controller. It holds a pointer to the next buffer to be opened. BIT 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 NEXT RESET X X X X X X X X 5.2.19 RADDL - Receive Burst Starting Address Low Register Normal Map R ead/Write Port = 2:18 T his is the lower 8 bits of a register pair us ed internally by the DMA controller as a s cratch pad for the burst addres s of the receive proces s. Writing to the R ADDH and R ADDL r egi s ter s whi l e communication is taking place may caus e errors in the DMA proces s . BIT 7 6 5 4 3 2 1 0 A07 A06 A05 A04 A03 A02 A01 A00 RADDL RESET X X X X X X X X 5.2.18 RADDH - Receive Burst Starting Address High Register Normal Map R ead/Write Port = 2:19 T his is the higher 8 bits of a register pair us ed internally by the DMA controller as a s cratch pad for the burst addres s of the receive proces s. Writing to the R ADDH and R ADDL r egi s ter s whi l e communication is taking place may caus e errors in the DMA proces s . BIT 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 RADDH RESET X X X X X X X X 5.2.20 RBEGIN - Receive Buffer Starting Address Register Linked-List Map R ead Port = 2:11 Linked-Lis t Map Write Port = 0:11 T his register holds the upper 8 bits of the s tarting address of the receive buffer des criptor table. T he lower 8 bits are as sumed to be zero. BIT 7 6 5 4 3 2 1 0 RB15 RB14 RB13 RB12 RB11 RB10 RB09 RB08 RBEGIN RESET X X X X X X X X 30 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 5.2.21 RCNTH - Receive Byte Count High Register Normal Map R ead Port = 0:1B T his regis ter contains the upper 8 bits of the receive unit's count of bytes received in the mos t recent frame. It is cleared by the receive unit at the s tart of reception. BIT 7 6 5 4 3 2 1 0 CT15 CT14 CT13 CT12 CT11 CT10 CT09 CT08 RCNTH RESET 0 0 0 0 0 0 0 0 5.2.23 RCON - Receive Configuration Register Normal Map R ead Port = 2:1C Normal Map Write Port = 0:1C Linked-List Map R ead Port = 2:1C Linked-List Map Write Port = 0:1C T he R eceive Configuration R egis ter defines optional behavior of the receive unit. It controls addres s recognition and the acceptance of abnor mal packets . T hes e bits can be s et independently, although the monitor mode takes precedence over the other bits . BIT 7 6 5 4 3 2 1 0 0 RCA MON PROM GROUP BROAD RUNTS SEP RCON RESET 0 0 0 0 0 0 0 0 5.2.22 RCNTL - Receive Byte Count Low Register Normal Map R ead Port = 0:1A T his regis ter contains the lower 8 bits of the receive unit's count of bytes received in the mos t recent frame. It is cleared by the receive unit at the s tart of reception. BIT 7 6 5 4 3 2 1 0 CT07 CT06 CT05 CT04 CT03 CT02 CT01 CT00 RCNTL RESET 0 0 0 0 0 0 0 0 Bit 7: Unused T his bit is unus ed in 83C795. When read, it always returns zero. Bit 6: RCA, Receive Abort Frame on Collision S etting this bit allows the receiver unit to abort reception of any frame in which the COL pin is active after the s tart of frame delimiter. R eception of any frame whos e prefix contains cons ecutive '0' bits is also aborted. Neither cause res ults in R XE being s et. It is not overridden by the S E P bit. T his bit was unused in the 83C690. Bit 5: MON, Check Addresses/CRC Without Buffering MON = 1 - T his bit enables the receive unit to check address es and CR C on incoming packets without buffering them to memory. T he Mis s ed Packet Counter (MPCNT ) will be incremented for each recognized packet. MON = 0 - T his is normal operation. Bit 4: PROM, Promiscuous Reception When PR OM = 1, this bit enables promiscuous reception of all frames having individual addres ses . 31 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS Bit 3: GROUP, Receive Multicast Frames When GR OUP = 1, this bit enables reception of all frames that: * have multicast addresses * pass the multicast address hashing filter Bit 2: BROAD, Receive Broadcast Frames When BR OAD = 1, this bit enables reception of all frames having a Broadcas t (all '1's ) des tination address . Bit 1: RUNTS, Receive Runts Frames When R UNT S = 1, this bit allows reception of frames having les s than 64 bytes , provided that they otherwis e meet the requirements of the 802.3 protocol. Bit 0: SEP, Save Errored Packets When S E P = 1, it directs the receive unit to s ave packets having CR C or frame alignment errors in the buffers . 5.2.24 RDOWNH - Buffer Room Remaining High Register Linked-List Map R ead/Write Port = 2:19 T his regis ter contains the upper 8 bits of a regis ter pair us ed by the DMA controller as a scratch pad for the buffer room remaining count during the reception proces s . Note Writing to these registers while communication is taking place may cause errors in the DMA process. BIT 7 6 5 4 3 2 1 0 RDOWNH A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X 5.2.25 RDOWNL - Buffer Room Remaining Low Register Linked-List Map R ead/Write Port = 2:18 T his regis ter contains the lower 8 bits of a regis ter pair us ed by the DMA controller as a scratch pad for the buffer room remaining count during the reception proces s . Note Writing to these registers while communication is taking place may cause errors in the DMA process. BIT 7 6 5 4 3 2 1 0 RDOWNL A07 A06 A05 A04 A03 A02 A01 A00 RESET X X X X X X X X 5.2.26 REND - Receive Buffer End Register Linked-List Map R ead Port = 2:12 Linked-Lis t Map Write Port = 0:12 T his regis ter holds the upper 8 bits of the firs t addres s beyond the end of the receive buffer descriptor table. T he lower 8 bits are as s umed to be zero. T he table lies between the numbers (R BE GIN * 256) and (R E ND * 256 - 1). R efer to page 88 for more details . BIT 7 6 5 4 3 2 1 0 REND RE15 RE14 RE13 RE12 RE11 RE10 RE9 RE8 RESET X X X X X X X X 32 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 5.2.27 RSTART - Receive Start Page Register Normal Map R ead Port = 2:11 Normal Map Write Port = 0:11 R eceive S tart Page regis ter points to the start of the receive buffer ring. Only A08-A15 are s pecified s i nce al l buffer s ar e aligned on 256-byte boundaries . R efer to page 88 for more information. BIT 7 6 5 4 3 2 1 0 RSTART A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X Bit 6: DIS, Receiver Disabled T his bit is s et when the receiver is in Monitor Mode. It is cleared when the receiver leaves Monitor Mode. Bit 5: GROUP, Group Address Recognized T his bit is s et when the recognized addres s was either a group addres s (multicas t) or broadcas t. It is cleared to indicate an individual (physical) addres s match. Bit 4: MPA, Missed Packet T his bit is s et when apacket intended for this s tation cannot be accepted by the device due to a lack of receive buffers or becaus e the device is in monitor mode. T he Mis s ed Packet Counter (MPCNT ) is als o incremented when this occurs . Bit 3: OVER, FIFO Overrun T his bit is s et when the receiver attempts to write into a F IF O that is already full. T his occurs when the DMA fails to keep up with the received data. Bit 2: FAE, Frame Alignment Error When FAE = 1, it indicates that the incoming packet did not end on a byte boundary and the CR C did not match at the las t byte boundary. T he Alignment E rror Counter is incremented when this condition occurs. Bit 1: CRC, CRC Error When this bit is s et, it indicates that the frame's computed CR C failed to corres pond with the CR C appended to the end of the frame. T his error also caus es the CR C Counter to be incremented. Bit 0: PRX, Packet Received Intact When set to '1', this bit indicates that a packet was received without error. T his means that CR C = FAE = OVE R = MPA = 0. 5.2.28 RSTAT - Receive Packet Status Register Normal Map R ead Port = 0:1C Linked-Lis t Map R ead Port = 0:1C T his regis ter reports the s tatus of the mos t-recently received packet. It categorizes any errors that were detected and reports on the type of addres s recognized. All bits are cleared at the s tart of reception except for DIS . BIT 7 6 5 4 3 2 1 0 RSTAT DRF DIS GROUP MPA OVER FAE CRC PRX RESET 0 0 0 0 0 0 0 0 Bit 7: DFR, Deferring IGSM T his bit is s et when the Interframe Gap S tate Machine (IGS M) is deferring. If the transceiver has as serted the CD line as a result of jabber, this bit will s tay s et indicating the jabber condition. 33 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.29 RSTOP - Receive Stop Page Register Normal Map R ead Port = 2:12 Normal Map Write Port = 0:12 T he R eceive S top Page R egis ter points to the firs t address beyond the las t receive buffer in the ring before wrapping around to the R S TART buffer. Only A08-A15 are specified s ince all buffers are aligned on 256-byte boundaries . BIT 7 6 5 4 3 2 1 0 RSTOP A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X 5.2.31 RTABL - Receive Buffer Table Pointer Low Register Linked-List Map R ead/Write Port = 0:18 T his regis ter contains the lower 8 bits for the regis ter pair us ed as a pointer to the receive buffer des criptors table. T hes e regis ters s hould be initializedto the s ame value as the R BE GIN regis ter when the descriptor table is created and thereafter left unaltered unles s the receiver buffer pool is rebuilt. F or more information, refer to page 89. BIT 7 6 5 4 3 2 1 0 A07 A06 A05 A04 A03 A02 A01 A00 RTABL RESET X X X X X X X X 5.2.30 RTABH - Receive Buffer Table Pointer High Register Linked-List Map R ead/Write Port = 0:19 T his regis ter contains the upper 8 bits for the regis ter pair us ed as a pointer to the receive buffer des criptors table. T hes e regis ters s hould be initializedto the s ame value as the R BE GIN regis ter when the descriptor table is created and thereafter left unaltered unles s the receiver buffer pool is rebuilt. F or more information, refer to page 89. BIT 7 6 5 4 3 2 1 0 RTABH A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X 5.2.32 STA0-STA5 - Station Address Registers STA Register STA0 STA1 STA2 STA3 STA4 STA5 Normal Map Port Address Read 1:11 1:12 1:13 1:14 1:15 1:16 Write 1:11 1:12 1:13 1:14 1:15 1:16 Linked-List Map Port Address Read 1:11 1:12 1:13 1:14 1:15 1:16 Write 1:11 1:12 1:13 1:14 1:15 1:16 T hes e 6 regis ters hold the node's individual s tation address . Table 5-11 s hows the bits definedfor these regis ters. 34 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 STA Registers STA0 STA1 STA2 STA3 STA4 STA5 RESET BIT 7 DA07 DA15 DA23 DA31 DA39 DA47 X BIT 6 DA06 DA14 DA22 DA30 DA38 DA46 X BIT 5 DA05 DA13 DA21 DA29 DA37 DA45 X BIT 4 DA04 DA12 DA20 DA28 DA36 DA44 X BIT 3 DA03 DA11 DA19 DA27 DA35 DA43 X BIT 2 DA02 DA10 DA18 DA26 DA34 DA42 X BIT 1 DA01 DA09 DA17 DA25 DA33 DA41 X BIT 0 DA00 DA08 DA16 DA24 DA32 DA40 X TABLE 5-11. STATION ADDRESS REGISTER BITS 5.2.33 TADDH - Transmit Burst Starting Address High Register Normal Map R ead/Write Port = 2:1B T his is the higher 8 bits of a register pair us ed internally by the DMA controller as a s cratch pad for the burst addres s of the trans mit proces s . Writing to the T ADDH and T ADDL R egis ters while communication is taking place may caus e errors in the DMA proces s . BIT 7 6 5 4 3 2 1 0 TADDH A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X 5.2.34 TADDL - Transmit Burst Starting Address Low Register Normal Map R ead/Write Port = 2:1A T his regis ter contains the lower 8 bits for a regis ter pair us ed internally by the DMA controller as a s cratch pad for the burst addres s of the transmit proces s . Writing to the T ADDH and T ADDL regis ters while communication is taking place may caus e errors in the DMA proces s . BIT 7 6 5 4 3 2 1 0 TADDL A07 A06 A05 A04 A03 A02 A01 A00 RESET X X X X X X X X 35 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.35 TBEGIN - Transmit Buffer Starting Address Register Linked-List Map R ead Port = 2:13 Linked-List Map Write Port = 0:15 T his register holds the upper 8 bits of the s tarting address of the transmit buffer des criptor table. T he lower 8 bits are as sumed to be zero. R efer to page 80 for more information. BIT 7 6 5 4 3 2 1 0 TBEGIN TB15 TB14 TB13 TB12 TB11 TB10 TB09 TB08 RESET X X X X X X X X 5.2.37 TCNTL - Transmit Frame Length Low Register Normal Map R ead Port = 2:13 Normal Map Write Port = 0:15 T his regis ter contains the lower 8 bits of a two-regis ter set that holds the byte count for the frame to be trans mitted. T his byte count mus t include the DA, S A, and data fields . If CR C generation is inhibited, this count mus t als o include the CR C field in the buffer. BIT 7 6 5 4 3 2 1 0 TCNTL L07 L06 L05 L04 L03 L02 L01 L00 RESET X X X X X X X X 5.2.36 TCNTH - Transmit Frame Length High Register Normal Map R ead Port = 2:16 Normal Map Write Port = 0:16 T his regis ter contains the upper 8 bits of a two-regis ter set that holds the byte count for the frame to be trans mitted. T his byte count mus t include the DA, S A, and data fields . If CR C generation is inhibited, this count mus t als o include the CR C field in the buffer. BIT 7 6 5 4 3 2 1 0 TCNTH L15 L14 L13 L12 L11 L10 L09 L08 RESET X X X X X X X X 5.2.38 TCON - Transmit Configuration Register Normal Map R ead Port = 2:1D Normal Map Write Port = 0:1D Linked-List Map R ead Port = 2:1D Linked-List Map Write Port = 0:1D T his regis ter controls loopback options and trans mitter mode operations . BIT 7 6 5 4 3 2 1 0 TCON 0 0 0 0 0 LB1 LB0 CRCN RESET 0 0 0 0 0 0 0 0 Bits 2-1: LB1, LB0, Loopback Test Selection T hes e two bits are decoded as s hown in Table 5-12. 36 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 LB1 LB0 0 0 1 1 0 1 0 1 Operation Normal (no loopback) Internal loopback (before MAN CODEC) Internal loopback, LOOP pin is high (after MAN CODEC) External loopback with LOOP pin low 5.2.40 TDOWNL - Transfer Count Low Register Linked-List Map R ead/Write Port = 2:1A T his regis ter contains the lower 8 bits for the regis ter pair us ed by the DMA controller as a s cratch pad for the bytes remaining to trans fer count during the transmis sion proces s . T hey can be acces sed for manufacturing test purpos es . Note Writing to these registers while communication is taking place may cause errors in the DMA process. BIT 7 6 5 4 3 2 1 0 TDOWNL A07 A06 A05 A04 A03 A02 A01 A00 RESET X X X X X X X X TABLE 5-12. LOOPBACK TEST SELECTION Bit 0: CRCN, CRC Generation Inhibition S etting this bit inhibits generation of CR C during trans miss ion of frame. T he us er is res pons ible for calculating the frame's CR C and placing it in the buffer in s uch a way that when the las t 4 bytes of the buffer are s hifted out, they form the correct CR C for the frame. Note that the s erializer s hifts bytes out LS B first whereas the CR C must be s hiftedMS B firs t. T he operation of the receiver is not affected by this bit. 5.2.39 TDOWNH - Transfer Count High Register Linked-List Map R ead/Write Port = 2:1B T his regis ter contains the upper 8 bits for the regis ter pair us ed by the DMA controller as a s cratch pad for the bytes remaining to trans fer count during the transmis sion proces s . T hey can be acces sed for manufacturing test purpos es . Note Writing to these registers while communication is taking place may cause errors in the DMA process. BIT 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 TDOWNH RESET X X X X X X X X 5.2.41 TEND - Transfer Buffer End Register Linked-List Map R ead Port = 2:14 Linked-List Map Write Port = 0:14 T his regis ter holds the upper 8 bits of the firs t addres s beyond the end of the trans mit buffer descriptor table. T he lower 8 bits are as s umed to be zero. T he table lies between (T BE GIN * 256) and (T E ND * 256 - 1). R efer to page 80 for more information. BIT 7 6 5 4 3 2 1 0 TE15 TE14 TE13 TE12 TE11 TE10 TE9 TE8 TEND RESET X X X X X X X X 37 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.42 TLEVEL - Transmit FIFO Track Register Normal Map R ead Port = 3:1E Linked-List Map R ead Port = 3:1E T his counter tracks the number of empty bytes in the trans mit FIFO. An empty F IF O has 10h in this counter. A full F IF O has 00h. BIT 7 6 5 4 3 2 1 0 -- -- -- CT04 CT03 CT02 CT01 CT00 TLEVEL RESET 0 0 0 0 0 0 0 0 5.2.44 TSTARTL - Transmit Start Page Low Register Normal Map R ead/Write Port = 3:15 Linked-List Map R ead/Write Port = 3:15 T his regis ter is the lower 8 bits of a regis ter pair that points to the as sembled packet to be transmitted. To retain compatibility with 83C690 drivers, the us er s hould s tart all frames on 256-byte boundaries and only write to the T S T ART H register. BIT 7 6 5 4 3 2 1 0 TSTARTL A07 A06 A05 A04 A03 A02 A01 A00 RESET 0 0 0 0 0 0 0 0 5.2.43 TSTARTH - Transmit Start Page High Register Normal Map R ead Port = 2:14 Normal Map Write Port = 0:14 T his regis ter is the higher 8 bits of a regis ter pair that points to the as s embled packet to be trans mitted. To retain compatibility with 83C690 drivers, the us er s hould s tart all frames on 256-byte boundaries and not write to T S T ART L. BIT 7 6 5 4 3 2 1 0 TSTARTH A15 A14 A13 A12 A11 A10 A09 A08 RESET 0 0 0 0 0 0 0 0 5.2.45 TSTAT - Transmit Status Register Normal Map R ead Port = 0:14 Linked-List Map R ead Port = 0:14 T he T rans mit S tatus R egis ter reports events that occur on the media at the end of packet tr ans mi s s ion. All bits are cleared prior to trans miss ion of a packet and are s et as needed. When ALT E GO = 1, the regis ter is cleared only at the beginning of a transmit chain and is s et after each packet has completed. BIT 7 6 5 4 3 2 1 0 TSTAT OWC CDH UNDER CRL ABORT TWC NDT PTX RESET 0 0 0 0 0 0 0 0 Bit 7: OWC, Out of Window Collision T his bit is set if a collision is detected more than one s lot time after the start of trans miss ion. T ransmis s ion is aborted under thes e conditions . 38 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 Bit 6: CDH, Collision Detect Heartbeat T his bit is s et to a '1' during transmis sion of each packet. It is s et to '0' if a collis ion is detected within 3.6 s ec of the end of each packet transmis sion. If no collision is detected within this window, it remains '1'. Bit 5: UNDERFIFO, FIFO or Buffer Underrun When this bit is s et, it means either: * a FIFO underrun condition has occurred. This condition results when the transmit unit attempts to read from an empty FIFO prior to receiving the transmit done flag from DMA. This means that the FIFO failed to supply enough data for the serializer to maintain frame generation. * a Buffer underrun has occurred. This condition happens when the transmit DMA accesses an address that is greater than or equal to the most recent host-written location in memory, provided that the Early Transmit Check feature is enabled. Bit 4: CRL, Carrier Sense Lost T his bit is s et if the carrier is los t during packet trans miss ion. Carrier s ense is monitored from its ris ing edge at the s tart of the outgoing frame's echo. T ransmis sion is not aborted upon loss of carrier. It is reported for s tatistical purpos es . Bit 3: ABORT, Abort Transmission T his bit is s et if the trans mis s ion is aborted due to exces s ive collis ions . Bit 2: TWC, Transmitted With Collisions T his bit is s et if the frame collided at leas t once with another frame on the network. It is not set for either out-of-window collis ions or exces s ive collis ion aborts . Bit 1: NDT, Non-deferred Transmission T his bit is s et if the frame was transmitted s ucces s fully without deferring. A deferred trans miss ion can only occur the firs t time an attempt is made to s end a packet. Collis ions are not deferred transmis sions . Bit 0: PTX, Packet Transmitted T his bit is s et to indicate trans mis s ion of a packet without exces s ive collis ions or a F IF O underrun. 5.2.46 TTABH - Transmit Buffer Pointer High Register Linked-List Map R ead/Write Port = 0:1B T his regis ter contains the higher 8 bits of the regis ter pair used as a pointer to the transmit buffer des criptors table. T hes e regis ters s hould be initialized to the same value as T BE GIN when the des criptor table is created, and not altered thereafter by the us er unles s the trans mit buffer pool is rebuilt. F or more information, refer to page 80. BIT 7 6 5 4 3 2 1 0 TTABH A15 A14 A13 A12 A11 A10 A09 A08 RESET X X X X X X X X 5.2.47 TTABL - Transmit Buffer Pointer Low Register Linked-List Map R ead/Write Port = 0:1A T his regis ter contains the lower 8 bits of the regis ter pair us ed as a pointer to the trans mit buffer des criptor table. T hes e regis ters s hould be initialized to the same value as T BE GIN when the des criptor table is created, and not altered thereafter by the us er unles s the trans mit buffer pool is rebuilt. BIT 7 6 5 4 3 2 1 0 TTABL A07 A06 A05 A04 A03 A02 A01 A00 RESET X X X X X X X X 39 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 5.2.48 RENH - Receive Enhancement Register Normal Map R ead/Write Port = 0:19 T he R eceive E nhancement R egis ter contains s everal bits required for the new receive features of the 83C795 chip. BIT 7 6 5 4 3 2 1 0 RENH -- -- -- -- -- REMPTY ERFBIT WRAPEN RESET 0 0 0 0 0 0 0 0 Bit 2: REMPTY, Ring Bit Empty When R E MPT Y = 1, this read-only bit indicates that the receive buffer ring has no completely received frames. Bit 1: ERFBIT, Early Receive Fail Bit When E R F BIT = 1 it indicates that an underrun has occurred during the reception of a frame. T he hos t clears this bit after reading the addres s where the failure occurred from the E R FA R egis ters. Bit 0: WRAPEN, Automatic Ring-Wrap Enable When WR APE N = 1 it enables the auto-wrapping feature. For more information on Automatic R ingWrap, refer to page 87. 40 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 ADDRESS 00 01 01 02 03 04 FUNCTION CONTROL EEROM EEROM IO PIPE LOW IO PIPE HIGH HW SUPP HW SUPP NAME CR RD ER WR ER IOPL IOPH BIT 7 RNIC STORE STORE IOP7 IOP15 BIT 6 MENB RC RC IOP6 IOP14 BIT 5 BIT 4 CR4 BIT 3 CR3 BIT 2 RP15 JMP2 EA2 IOP2 IOP10 ISTAT BIT 1 RP14 JMP1 EA1 IOP1 IOP9 BIT 0 RP13 JMP0 EA0 IOP0 IOP8 -- EA4 EA4 IOP5 IOP13 ETHER UNLOCK JMP3 UNLOCK EA3 IOP4 IOP12 HOST16 IOP3 IOP11 RD HWR SWH WR HWR SWH BPR ICR REV IOPA LAN0 LAN1 LAN2 LAN3 LAN4 LAN5 BDID CKSM IAR RAR BIO GCR ERFAL M16EN MCTEST CHIP3 IOPA7 LN07 LN15 LN23 LN31 LN39 LNMSB BDID7 CHK7 -- IA15 HRAM FINE ERFA7 ERFA15 -- -- BP15 STAG CHIP2 IOPA6 LN06 LN14 LN22 LN30 LN38 LN46 BDID6 CHK6 -- IA14 RA17 BA17 ERFA6 -- NUKE PNPJMP GPOE -- BP14 IOPAV CHIP1 IOPA5 LN05 LN13 LN21 LN29 LN37 LN45 BDID5 CHK5 -- IA13 RAMSZ1 BIOSZ1 OWS ERFA5 -- BP13 IOPEN CHIP0 IOPA4 LN04 LN12 LN20 LN28 LN36 LN44 BDID4 CHK4 -- IA8 RAMSZ0 BIOSZ0 RIPL ERFA4 ERFA12 -- -- REV2 IOPA2 LN02 LN10 LN18 LN26 LN34 LN42 BDID2 CHK2 -- IA6 RA15 BA15 IR0 ERFA2 -- SOFT1 GPOE SOFT0 EIL REV0 IOPA0 LN00 LN08 LN16 LN24 LN32 LN40 BDID0 CHK0 PNPIOP PNPBOOT RA13 BA13 LIT PNPEN ERFA8 05 06 07 BIOS PAGE INT CONTROL REVISION IO PIPE ADDR -- SINT REV3 IOPA3 LN03 LN11 LN19 LN27 LN35 LN43 BDID3 CHK3 -- IA7 RA16 BA16 IR1 ERFA3 ERFA11 MASK2 MASK1 REV1 IOPA1 LN01 LN09 LN17 LN25 LN33 LN41 BDID1 CHK1 -- IA5 RA14 BA14 GPOUT -- 08 SWH=0 09 SWH=0 0A SWH=0 0B SWH=0 0C SWH=0 0D SWH=0 0E SWH=0 0F SWH=0 08 SWH=1 0A SWH=1 0B SWH=1 0C SWH=1 0D SWH=1 0E SWH=1 0F SWH=1 LAN ADDR0 LAN ADDR1 LAN ADDR2 LAN ADDR3 LAN ADDR4 LAN ADDR5 BOARD ID CHECKSUM I/O ADDRESS RAM BASE BIOS BASE GEN CONTROL ERF ADDR LOW GENERAL CNTL2 GCR2 XLENGTH IR2 ERF ADDR HIGH ERFAH ERFA14 ERFA13 ERFA10 ERFA9 TABLE 5-13. HOST INTERFACE REGISTER SUMMARY 41 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS REGISTER ALICNT BOUND CMD COLCNT CRCCNT CURR CURRH CURRL DCON ENH ERWCNT GROUP0 GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 GROUP6 GROUP7 INTMASK INTSTAT MANCH MPCNT NEXT RADDH RADDL RBEGIN RCNTH RCNTL RCON RDOWNH RDOWNL REND RENH RSTART RSTAT RSTOP RTABH RING 0:1D -- LINKED 0:1D -- -- BIT 7 CT7 A15 BIT 6 CT6 A14 PS0 T9 CT6 CURR14 BIT 5 CT5 A13 0 T8 CT5 CURR13 BIT 4 CT4 A12 BIT 3 CT3 A11 BIT 2 CT2 A10 BIT 1 CT1 A09 STA CT1 CT1 CURR09 BIT 0 CT0 A08 STP CT0 CT0 CURR08 0:13 0:13 -- 0:15 -- 0:1E -- -- -- -- -- X:10 X:10 X:10 X:10 PS1 0:15 -- 0:1E -- -- T10 CT7 CURR15 ENETCH DISETCH TXP T7 CT4 CURR12 CT3 CT3 CURR11 CT2 CT2 CURR10 1:17 1:17 -- 1:17 1:17 CURR15 CURR14 CURR13 CURR12 CURR11 CURR10 CURR09 CURR08 0:13 0:13 CURR07 CURR06 CURR05 CURR04 CURR03 CURR02 CURR01 CURR00 1 1 ERW10 GA06 GA14 GA22 GA30 GA38 GA46 GA54 GA62 ERWE ERW SEL CT6 A14 A14 A06 A14 CT14 CT06 RCA A14 A06 A14 -- A14 DIS A14 A14 0 ALTEGO ERW9 GA05 GA13 GA21 GA29 GA37 GA45 GA53 GA61 CNTE CNT 0 CT5 A13 A13 A05 A13 CT13 CT05 MON A13 A05 A13 -- A13 GROUP A13 A13 0 SLOT1 ERW8 GA04 GA12 GA20 GA28 GA36 GA44 GA52 GA60 OVWE OVW 0 SLOT0 ERW7 GA03 GA11 GA19 GA27 GA35 GA43 GA51 GA59 TXEE TXE 0 EOTINT ERW6 GA02 GA10 GA18 GA26 GA34 GA42 GA50 GA58 RXEE RXE LNK CT2 A10 A10 A02 A10 CT10 CT02 BROAD A10 A02 A10 0 -- ERW5 GA01 GA09 GA17 GA25 GA33 GA41 GA49 GA57 PTXE PTX RLED CT1 A09 A09 A01 A09 CT09 CT01 RUNTS A09 A01 A09 1 SBACK ERW4 GA00 GA08 GA16 GA24 GA32 GA40 GA48 GA56 PRXE PRX XLED CT0 A08 A08 A00 A08 CT08 CT00 SEP A08 A00 A08 WRAPEN A08 PRX A08 A08 2:1E 0:1E 2:1E 0:1E 0 2:17 2:17 2:17 2:17 0 0:18 0:18 0:18 0:18 ERW11 1:18 1:18 1:18 1:18 GA07 1:19 1:19 1:19 1:19 GA15 1:1A 1:1A 1:1A 1:1A GA23 1:1B 1:1B 1:1B 1:1B GA31 1:1C 1:1C 1:1C 1:1C GA39 1:1D 1:1D 1:1D 1:1D GA47 1:1E 1:1E 1:1E 1:1E GA55 1:1F 1:1F 1:1F 1:1F GA63 2:1F 0:1F 2:1F 0:1F 0 0:17 0:17 0:17 0:17 RST 3:1F 3:1F 3:1F 3:1F MANDIS 0:1F -- 0:1F -- -- -- -- -- -- CT7 A15 A15 A07 ENAPOL TPOL CT4 A12 A12 A04 A12 CT12 CT04 PROM A12 A04 A12 -- A12 MPA A12 A12 CT3 A11 A11 A03 A11 CT11 CT03 GROUP A11 A03 A11 -- A11 OVER A11 A11 2:15 2:15 -- 2:19 2:19 -- 2:18 2:18 -- -- -- 0:1B -- 0:1A -- -- -- -- -- -- -- -- -- 2:11 0:11 A15 CT15 CT07 2:1C 0:1C 2:1C 0:1C 0 2:19 2:19 A15 2:18 2:18 A07 2:12 0:12 A15 -- 0:19 0:19 2:11 0:11 -- 0:1C -- -- -- 2:12 0:12 -- -- 0:1C -- REMPTY ERFBIT A10 FAE A10 A10 A09 CRC A09 A09 A15 DFR A15 -- 0:19 0:19 A15 TABLE 5-14. LAN CONTROLLER REGISTER SUMMARY 42 ETHERNET SYSTEM CONTROLLER REGISTERS 83C795 REGISTER RTABL STA0 STA1 STA2 STA3 STA4 STA5 TADDH TADDL TBEGIN TCNTH TCNTL TCON TDOWNH TDOWNL TEND TLEVEL TSTARTH TSTARTL TSTAT TTABH TTABL -- RING -- LINKED BIT 7 BIT 6 A06 DA06 DA14 DA22 DA30 DA38 DA46 A14 A06 A14 L14 L06 -- A14 A06 TE14 -- A14 A06 CDH A14 A06 BIT 5 A05 DA05 DA13 DA21 DA29 DA37 DA45 A13 A05 A13 L13 L05 -- A13 A05 TE13 -- A13 A05 UNDER A13 A05 BIT 4 A04 DA04 DA12 DA20 DA28 DA36 DA44 A12 A04 A12 L12 L04 -- A12 A04 TE12 CT04 A12 A04 CRL A12 A04 BIT 3 A03 DA03 DA11 DA19 DA27 DA35 DA43 A11 A03 A11 L11 L03 -- A11 A03 TE11 CT03 A11 A03 ABORT A11 A03 BIT 2 A02 DA02 DA10 DA18 DA26 DA34 DA42 A10 A02 A10 L10 L02 LB1 A10 A02 TE10 CT02 A10 A02 TWC A10 A02 BIT 1 A01 DA01 DA09 DA17 DA25 DA33 DA41 A09 A01 A09 L09 L01 LB0 A9 A01 TE09 CT01 A09 A01 NDT A09 A01 BIT 0 A00 DA00 DA08 DA16 DA24 DA32 DA40 A08 A00 A08 L08 L00 CRCN A8 A00 TE08 CT00 A08 A00 PTX A08 A00 0:18 0:18 A07 1:11 1:11 1:11 1:11 DA07 1:12 1:12 1:12 1:12 DA15 1:13 1:13 1:13 1:13 DA23 1:14 1:14 1:14 1:14 DA31 1:15 1:15 1:15 1:15 DA39 1:16 1:16 1:16 1:16 DA47 2:1B 2:1B -- 2:1A 2:1A -- -- -- -- A15 A07 -- 2:13 0:15 A15 2:16 0:16 -- 2:15 2:15 -- -- -- -- 3:1E -- -- -- -- -- L15 L07 2:1D 0:1D 2:1D 0:1D -- 2:1B 2:1B A15 2:1A 2:1A A07 2:14 0:14 TE15 3:1E -- -- A15 2:14 0:14 -- 0:14 -- -- -- -- -- 3:15 3:15 3:15 3:15 A07 0:14 -- OWC 0:1B 0:1B A15 0:1A 0:1A A07 TABLE 5-14. LAN CONTROLLER REGISTER SUMMARY (cont.) 43 83C795 HOST INTERFACE SECTION 6.0 HOST INTERFACE SECTION T he Hos t Interface is a configurable interface between an Indus try S tandard Architecture bus (like IBM PC/XT /AT ) and the LAN controller with its buffer memory. T he interface is a s lave peripheral with s hared R AM and s upport for an Initial Program Load R OM. T he bas ic functions of the hos t interface section are the: * Address decode * Memory address generation * Retrieval and storage of configuration parameters and LAN address * Interrupt mapping and control * Control over certain HW functions for support circuitry 6.1 MEMORY CACHE hos t addres s . T he s econd, called the B uffer Counter, is usedto generate the addres s to the local buffer R AM. T he s ame data F IF O is us ed for both reads and writes res ulting in two different modes of operation: R ead Mode and Write Mode. R E AD MODE If the hos t address does not equal the value in the Hos t Counter, then both counters are loaded with the incoming addres s . T hen the cache is filled with data from the buffer R AM a byte at a time by incrementing the Buffer Counter. T he hos t access is s talled during this time by driving the IOR DY s ignal low. Once the cache has a valid word of data from the buffer R AM, the IOR DY line is driven high. T his s ignals the host that the data is valid, and the host, in turn, ends the access . Once the hos t has finis hed, the Hos t Counter is incremented (the increment s tep will be either 1 or 2 depending on whether the hos t access was for a byte or for a word), and the F IF O pointers are updated. T he cache continues to fill with data as long as there is room in the F IF O. If the hos t addres s matches the value in the Hos t Counter (and there is valid data in the cache), the read can be s erviced immediately. WR IT E MODE T he Write Mode is handled like the R ead Mode except that the data moves in the oppos ite direction through the F IF O. Als o, if an addres s mis s occurs in write mode, the cache mus t firs t flush all valid data in the F IF O out to the buffer R AM before loading new values into the addres s counters. T he IOR DY signal is us ed when the cache needs to s tall a hos t access . T his s ignal is outputted by a high current, tri-s tatable driver which is normally turned off between acces s es to the board. It drives low to indicate that the board is not IOR DY and drives high when making the trans ition from 'not ready' to 'ready'. When the acces s completes , the IOR DY line is tri-stated by the ending of the host's s trobes . F igure 6-1 depicts the memory cache arrangement. T he memory cache in the 83C795 cons is ts of a 4-byte-deep F IF O which s erves as an intermediate buffer between the IS A bus and the local buffer R AM. F or read operations , the cache acts as a s mall prefetch buffer which fills itself with data from locations in the buffer R AM that depend on the address of the las t data location read by the hos t. F or write operations , the cache acts as several temporary regis ters that can be as ynchronous ly written by the host, then s ynchronously flus hed to buffer R AM as time permits . T his method provides s everal advantages over previous methods : * Host accesses to shared memory can be treated more like register accesses, thus simplifying zero-wait state timing. * A single 8-bit wide buffer RAM is used but the chip can accommodate 8- or 16-bit accesses by the host. * Asynchronous arbitration between the host and the DMA controller for access to the buffer RAM is not necessary. In addition to the data F IF O, the cache requires two address counters for its operation. T he firs t, called the Host Counter, is compared with the incoming 44 HOST INTERFACE SECTION 83C795 FIGURE 6-1. MEMORY CACHE ARRANGEMENT 6.1.1 Zero Wait State Response to Host 3. T he Z ero Wait S tate s ignal tells the microproces s or that it can complete the pres ent bus cycle without ins erting any additional wait cycles . F or 16-bit memory acces s , this means zero wait s tates are ins erted by the host bus logic and the access cycle completes in 2 bus clocks. When as s erted for an 8 bit memory acces s , an IS A bus automatically ins erts the minimum of 2 wait s tates . T he response algorithm for the Z WS line depends upon the memory width, the hos t acces s type and whether the board has been enabled to act as a 16-bit device. T he appropriate ZWS res pons e logic is selected on the basis of the BPR .M16E N control bit and whether the board is in an 8- or 16-bit slot. T he memory cache can accommodate zero wait s tate timing if the following conditions are met: 1. 2. The type of host access matches the current mode of the cache, The host address matches the value in the host counter, and The cache either contains at least one valid data word for reads or has room for at least one more word for writes. F or writes , zero wait s tates are als o always poss ible if the cache is in read mode, or if it is currently empty. T here is a Z ero Wait E nable bit in one of the hos t interface regis ters (CR .Z WS E N) which can be us ed to prevent the 83C795 from as s erting the Z ero Wait S tate s ignal. 6.1.2 Staggered Address Transfers S taggered addres s transfers occur when the hos t attempts 16-bit data trans fers from s ys tem memory to the local buffer R AM and finds that the address of the sys tem data differs from the local addres s in the leas t significant bit (one is even, one is odd). In cons equence, the IS A bus forbids 16-bit acces s es to odd locations and breaks the trans fer into two 8-bit cycles which run cons iderably s lower. To overcome this on the 795: 45 83C795 HOST INTERFACE SECTION 1. 2. Make sure the system address is even. If the address comes out odd, transfer one byte. Set the STAG bit (ICR.6). This forces a '1' into bit 0 of the Buffer Counter when the address is loaded NOTE This only happens on a cache miss. T his makes it pos sible for the host to perform an even-to-even transfer, but the internal addres s to the local R AM is trans formed to an odd addres s . 6.1.3 Operation on Micro-Channel Adapters Do not use this chip for micro-channel applications . A future variant may be created with the necess ary interface logic. 6.2 I/O-MAPPED PIPE T he I/O-mapped pipe provides another method for acces s ing the local buffer R AM. When enabled, all memory acces s es take place through two I/O regis ters in the hos t interface I/O s pace (IOPL and IOP H). T he data in thes e two I/O locations corres ponds to the the location in the buffer memory indicated by the Buffer Counter. When run in this mode, the memory-space addres s decoders are disabled, s o the adapter will not us e any hos t memory space for the buffer R AM. T he mechanis m us ed by the I/O-pipe is similar to that us ed by the memory cache except for address DECODER BUFFER MIN BASE C0000H handling. In this method, the addres s is loaded into the Buffer Counter by performing two cons ecutive writes to the IOPA regis ter. T he firs t write stores the lower half of the address into a temporary register. T he second write s tores data directly into the upper half of the buffer counter and moves the temporary regis ter into the lower half. Any acces s to the chip between the two writes will cause the s tate machine to not load the address . T he Host Counter is not us ed during this proces s . To us e the I/O-pipe, the IOPE N bit (ICR .4) mus t be s et to 1, and the ME NB bit (CR .6) mus t be s et to 0. All 8-bit trans fers must take place through IOPL only. Als o, it is imperative that when s witching from R ead Mode to Write Mode, the addres s mus t be reloadedeven if the counter holds the correct value. 6.3 ADDRESS DECODERS T hree addres s decoders are us ed to detect hos t acces s es to the buffer memory, I/O regis ters, and IPL R OM. T hese decoders obs erve the S A19-S A05 lines to decode acces s within a range of addres s es (a window). T he buffer and IPL R OM decoders allow placement of their res pective windows on any 8K boundary between C0000H and E F F F F H regardles s of window size. T his allows windows to s tart on even or odd 8K boundaries . T he R AM and IPL R OM are s crollable (and therefore can be paged) through their programmable window s ize as s hown in Table 6-1 below. MAX BASE EE000H INCREMENT 2000H WINDOW SIZES 8K 16K 32K 64K* DISABLED 8K 16K 32K DISABLED 32 Bytes IPL ROM C0000H EE000H 2000H I/O BASE 0200H E3E0H 20H, 2000H TABLE 6-1. HOST INTERFACE ADDRESS DECODERS * Plug and Play cannot utilize this window s ize. 46 HOST INTERFACE SECTION 83C795 B ecaus e of the 16-bit memory mechanis m employed in IS A bus es , do not allow the memory window to overlap the DF F F F H to E 0000H boundary when us ing 16-bit memory. If the boundary cros s es , hos t memory acces s es to portions above E 0000H are made into 8-bit cycles . Note Use caution when overlapping the ROM and RAM windows if the RAM is 16-bit wide and both windows are enabled. With 16-bit access enabled, the M16CS is asserted for all accesses within the same 128K address block as the RAM base window address. Should the access actually be intended to the ROM, the host falsely expects the ROM to return 16-bit data. THIS CAN CRASH THE OPERATING SYSTEM. To avoid such problems on 16-bit boards, copy ROM code to system RAM and disable the ROM window. Alternatively, map the ROM into other 128K address block. Program control enables buffer memory decoding through a regis ter in the host interface section. When connected to a 16-bit bus , this comparis on is qualified by ME MR , ME MW, and the inverse of AE N. When connected to an 8-bit bus , the qualification is by S ME MR , S ME MW, and the invers e of AE N. T he buffer memory window s ize is program-s electable as 8K, 16K, 32K, 64K bytes or dis abled. T he buffer bas e addres s can be s et to any 8K boundary from C0000H through E E 000H. B y s etting a bit in the R AM Addres s R egis ter (R AR .HR AM), the decoded buffer range can be changed to the range F C0000h - F E E 000h. (T his range is not pos sible when us ing Plug and Play.) When connected to a PC/XT bus having no LA lines , it is required that the BPR .M16E N be kept a zero (inactive). T he IPL R OM decoding is enabled by program control through the BIO register in the hos t interface s ection. Decoder qualification is by S ME MR and an inverted AE N. R OM window s iz e is program s electable from 8K, 16K, 32K bytes or dis abled. T he R OM window placement in hos t memory s pace FIGURE 6-2. OVERLAPPING ADDRESS STRUCTURE 47 83C795 HOST INTERFACE SECTION is programmable on any 8K boundary from C0000H to E E 000H. Where R OM and R AM decoding overlaps , R OM takes precedence. F igure 6-2 s hows how the overlapping addres s s tructure works . You can relocate R AM and R OM bas e addres s es in tandem above 1M (100000H) with the application of an external cas caded addres s decoder. T his is illustrated in F igure 6-3. Note Relocation of the memory windows in this way is not supported when Plug and Play is enabled. 6.3.1 Memory Address Generation R OMs and buffer memories larger than their programmed windows can be scrolled (paged) by us ing programmable addres s modifiers (adders ) that lie between the host addres s and the R OM or buffer memory. T hese addres s modifiers can add independently to either addres s any of the following values and expos e different parts of the targeted memory within the window: 0000H 2000H 4000H 6000H 8000H A000H C000H E000H T he lower addres s lines (S A12-0) from the hos t are multiplexed with the DMA address lines to generate part of the memory addres s . T wo potential memory addres s es are generated by s ubtracting the res pective R AM and R OM bas e addres s bits (17-13) fr om S A17-S A13, then adding the R P15-R P13 field of the CR R egister for the R AM FIGURE 6-3. EXTERNAL CASCADED ADDRESS DECODER 48 HOST INTERFACE SECTION 83C795 addres s or the B P15-B P13 field of the B PR R egis ter for the R OM addres s . Depending on whether the buffer memory or the R OM window is being access ed, one of those two pos s ible sums becomes MA15-MA13 to the memory cache counters. R efer to F igure 6-4 for an illus tration of the address generation path. FIGURE 6-4. ADDRESS GENERATION PATH 49 83C795 HOST INTERFACE SECTION 6.3.2 I/O Address Decode 6.4 BUS CONTROL SIGNALS T he I/O addres s decoder compares the sys tem address lines S A15-S A13 and S A8-S A5 against a programmable value. S A9 is compared to '1'. T he lower group of lines gives a window size of 32 bytes located on 32-byte boundaries over the range of 200H to 3E 0H. T he comparis on with upper address bits allows the window to be located outs ide the base I/O area in the event there are multiple LAN cards on the s ame backplane. T his comparis on is qualified by the IOR , IOW, and the invers e of the AE N lines . I/O bas e location pos sibilities are: 0200, 0220, 0240, ..., 03E0 2200, 2220, 2240, ..., 23E0 4200, 4220, 4240, ..., 43E0 ... E200, E220, E240, ..., E3E0 Note Only the first base location option is supported by Plug and Play. T he I/O addres s is further decoded to res olve between the L AN controller and regis ters as sociated with the hos t interface bas ed on the A4 address line. 6.3.2.1 PC-98 Bus Support T wo s ignals control much of the bus activity. T hey are I/O Channel R eady (IOR DY) and Z ero Wait S tate (Z WS ). E ach is explained below. 6.4.1 IORDY T he IOR DY output is a high current, tri-s tate driver which is normally turned off between acces s es to the board. It will actively drive low to indicate that the board is not IOR DY and drives high when making the trans ition from 'not ready' to 'ready'. Acces s to the internal regis ters of the L AN controller is arbitrated by the LAN controller. T his arbitration is transparent to the hos t. When host acces s is completed, IOR DY is tri-stated by the ending of the hos t's s trobes . 6.4.2 Zero Wait State Response To Host T he Z ero Wait S tate (Z WS ) s ignal tells the microproces s or that it can complete the present bus cycle without ins erting any additional wait cycles . T he res pons e algorithm for the Z WS line depends on the memory width, the host access type, and whether the board has been enabled to act as a 16-bit device. T he appropriate type of Z WS res pons e logic is s elected on the bas is of memory width and the M16E N control bit state. T here is a Z ero Wait E nable bit in one of the hos t interface regis ters (CR .Z WS E N) which can be us ed to prevent the 83C795 from as s erting the Z ero Wait S tate s ignal. T his feature allows the I/O addres s decoding to be changed to s upport the NE C PC-98 bus. T his is done by installing JUMPE R 7, which connects an external resistor between MA7 and ground. When enabled, the S A9-S A1 lines replace the S A8-S A0 lines , the S A12-S A10 lines mus t be all 1's , and the S A0 line mus t be zero for an I/O access to occur. T his remapping only affects I/O acces s es and leaves memory decoding unchanged. 50 HOST INTERFACE SECTION 83C795 6.5 MEMORY BUS STRUCTURE AND CONFIGURATION Memory Bus Width Control host is access ing a device other than 83C795 within the s ame addres s range. To allow finer resolution for the M16CS decode, there is an optional means of including the decoding of S A16-S A13 lines in the generation of the M16CS res pons e. T his can be enabled by the FINE 16 bit of the Memory Page R egis ter. Becaus e the S Alines are not guaranteed s table as early as LA lines , this form of decoding can lead to erroneous res ults . Be careful when you us e this method. To avoid bus width conflicts between buffer memory and the R OM as well as conflicts with other cards in the s ystem, the 16-bit response s hould be turned on by s oftware only when that s oftware can guarantee that no access to the R OM is taking place and that the only acces s es within the 128K memory range are to 16-bit devices . T his may mean ens uring that no acces s to any other card can take place. In exis ting drivers , this is done by performing all 16-bit trans fers within interrupt s ervice routines that keep all other interrupts disabled during the trans fer. Take s pecial care when writing IPL R OM code. If the code actually gets executed out of R OM, the R OM can potentially be configured within the same 128K block. T he best advice is to copy code from R OM to s ys tem memory outs ide the block or to write code that does not enable 16-bit trans fers . T he Hos t is provided with the ZWS s ignal in accordance with whether the memory cache can accommodate the trans fer. T he timing of this signal is dependent upon the width of the trans fer being performed with the host. To meet the memory bandwidth required by the IS A bus, it is necess ary to implement the buffer memory 6.5.1 Becaus e of the 83C795's memory cache, the width of the memory path is fixed at 8 bit. By means of the memory cache, the I/O pipe can service either an 8-bit or 16-bit hos t acces s . T he Hos t and hos t interface logic are programmed for a s pecific memory width by s etting bit 7 in the BIOS Page R egis ter, M16E N. (S ee page 17 for more on this bit.) T he 83C795 calculates the width of the hos t bus by observing the ME MR line for trans itions . An internal flag (E E R OM.HOS T 16) is s et to indicate a 16-bit host bus after 2 ris ing edges are s een on this pin. When connected to an 8-bit hos t, this pin is left unconnected or is tied to VDD and s hould not have any trans itions . 6.5.2 16-Bit Response To Host Access T he BPR .M16E N bit in the BIOS Page R egis ter tells the hos t interface logic whether to make the L AN adapter res pond as a 16-bit or an 8-bit peripheral to the hos t. T he 83C795 res ponds to either hos t bus width. When the hos t acces s es memory, an addres s comparator within the 83C795 looks at the LA23-L A17 lines to determine if the 83C795's memory territory is being acces s ed. If it is and if MPR .M16E N is s et, the M16CS line is activated to tell the hos t to run a 16-bit trans fer cycle. When this decision is bas ed only on the LA addres s lines, it is poss ible that the M16CS will be s ent out when the 51 83C795 HOST INTERFACE SECTION with fast (35 ns ec) R AMs . F or more details , s ee the AC timing s pecs in S ection 10. 6.6 INTERRUPT REQUEST CONTROL LOGIC T here are two s ources of interrupt reques ts to the host: the LAN Controller and a programmable bit (S INT ) in the ICR regis ter. T he LAN controller s ection provides for the mas king, polling, and clearing of its individual interrupt conditions . T he s um of the masked LAN interrupt conditions is 'OR 'ed with the programmable interrupt from the host interface section (S INT ) and gated by the E IL bit from the ICR regis ter prior to turning on one of the s even program-s electable tri-state drivers . T he driver s election is made via bits in the GCR register. Interrupt dis abling s hould be accomplis hed via the ICR .E IL bit, not by changing the interrupt level to '0', becaus e during the transition from an active level to tri-s tate, fals e interrupts may be generated. T he Interrupt R equest Control logic is depicted in F igure 6-5. FIGURE 6-5. INTERRUPT CONTROL LOGIC 52 HOST INTERFACE SECTION 83C795 6.7 EEROM CONTROLLER AND ITS UTILIZATION T he 83C795 is des igned to operate in conjunction with a s erial E E R OM memory that s tores the configur ation of the hos t interface and the permanently-as signed LAN s tation addres s . It can reduce the number of jumpers needed on a board and allows for reconfiguration without removing the board from the s ys tem. T he E E R OM is us ed to initialize s ome of the hos t interface configuration regis ters at res et time. 6.7.1 Initialization Of 83C795 At the end of reset, thes e INIT pins are s ampled and latched. One of thes e combinations determines whether the E E R OM is read into the hos t interface regis ter s . Or dinarily, the 83C795 loads its configuration regis ters from E E R OM, but s election of one s pecial combination of jumpers (when all INIT s are pulled down) provides a means of bypas s ing the E E R OM load to allow rapid s imulation and tes ting of the device. Utilize the bypas s mode to produce a less expensive adapter des ign which does not retain configuration or address permanently. T here is als o a means of accelerating the E E R OM clock and as s ociated E E R OM interface pins (E E DO, E E CS , LLE D, R LE D) for tes t purposes . LLE D is connected to the E E R OM clock pin (E E S K) and is normally the primary clock (20 MHz) divided down by 128 during E E R OM acces s es. T he IOR and IOW pins are latched on the ris ing edge of R E S E T. If both are active (low) at the s ame time, the clock accelerates to 10 MHz. To res tore the normal 156 kHz clock rate, the chip is reset without activating IOR or IOW. R LE D is connected to the E E R OM's data-in pin, E E DI. U nles s bypas s ed, the E E R OM data is read automatically into the hos t interface regis ters jus t after the 83C795 is res et. T his takes approximately 2 milliseconds . During this time, memory, R OM, andregis ter acces s is dis abled. I/O acces s es to any host interface regis ter return garbage except for bit 6, which will return '1' until the regis ters are loaded at which time bit 6 returns '0'. To determine when the initial load of regis ters is completed, poll the E E R R egis ter. If the R E CALL bit (Bit 6) equals 0, the initial load is complete. T he regis ters s tart out with their res et values and are changed one regis ter at a time as the E E R OM is read out. T he buffer memory is always dis abled upon reset and mus t be enabled by s oftware. T he first time an E E R OM is powered up, it has random data. T he 83C795 can be acces s ed at known initial addres s es if a special s etting of the INIT pins is chos en when R E S E T pin is active. T his is explained in more detail in the following s ection. Activation of the res et pin forces the internal s tate of the 83C795 to a known value. T here is a group of option bits that can be configured by attaching res is tive pull-downs to four of the memory address output lines (MA09-MA00). T hes e pins are s ometimes referred to as the INIT pins . T hey s till perform their function as memory addres s lines but als o act as input pins during the R E S E T proces s . E ach pin has a high impedance internal pull-up res is tor that caus es the pin to read as '1' unles s a lower-impedance external pull-down resistor brings the natural s tate of the line to a logic '0' level. It is expected that an application of this chip would use a s et of jumpers to s electively connect thes e pins to the external pull-downs , as s hown in Table 6-2 below. Jumpers Pins Effect These jumpers are installed to mark 0 bits JMP0-3 MA0-3 EEROM Config. field, bits 0-3. These jumpers are installed to activate features JMP4 MA4 Switching PS HIDUTY option. JMP5 MA5 Switching PS output from GPOUT. JMP6 MA6 Plug and Play logic enable. JMP7 MA7 NEC PC-98 Bus support. JMP8 MA8 Drive 20 MHz clock out T L E D pin. JMP9 MA9 Use 83C790 Chip ID field instead of the 83C795 ID field. TABLE 6-2. JUMPER EXAMPLE 53 83C795 HOST INTERFACE SECTION 6.7.2 Retrieval And Storage Of Host Configuration Registers EEROM Interface Overview Reset Recall 0 0 1 0 1 X No Recall Action Recall from bank 'EA' into LAN ADDR registers Recall from bank '6' into LAN ADDR registers and from bank 'INIT' into configuration registers. 6.7.2.1 An external 9356 s erial E E R OM is us ed to s tore up to 256 bytes of data. It takes about 2 ms to read all 16 regis ters after the end of the res et puls e. It takes about 200 ms to s tore the E E R OM. T he LAN Controller s hould not be online (trans mitting or able to receive) while E E R OM recall or s tore operations are ongoing, nor s hould any of the regis ters in the L AN controller or hos t interface s ection be acces s ed during that time. Unpredictable res ults may occur becaus e the internal data bus s es will be s upporting the data movement to or from the E E R OM during that time interval. An exception to this rule is made in the cas e of the E E R regis ter, which may be polled to determine when the recall or s tore operation completes . When the E E R regis ter is read, the E E R .S T O and E E R .R C bits are vis ible to the hos t. Other bits from that regis ter are meaningful only when there is no ongoing E E R OM operation. All 256 bytes of E E R OM can be written to and read from. T hey are read into the LAN Addres s regis ters 8 bytes at a time. Once there, they can be changed and stored. T he E E R OM controller can be operated under program control to do partial retrievals from and s ave configuration data into the E E R OM. E E R OMs have a limited number of s torage cycles . T he s tore operation s hould only take place at initial board configuration or at initial ins tallation in a customer's computer. 6.7.2.2 EEROM Recall Operation Details TABLE 6-3. EEROM RECALL OPERATIONS T he recall of hos t interface configuration regis ters (addres s es 08-0F h, S WH=1) are done from the bank s elected by 4 INIT jumpers . Table 6-4 defines which bank of configuration regis ters corresponds to each arrangement of the INIT pins. INIT: Bank Notes MA3-0 0000 NONE All pins jumpered to ground. This is the bypass condition. 0001 14 0010 13 0011 12 0100 11 0101 10 0110 9 0111 8 1000 7 1001 6 Initial recall defaults: I/O = 280h ROM= disabled at C0000h RAM = 8K at C8000h INT = 0 (no interrupt mapped) LIT = disabled, GPOUT = 0 Configuration Registers (IAR, RAR, BIO, GCR, GCR2) are not recalled after this RESET. 1010 1011 1100 1101 1110 1111 5 4 3 2 1 0 All recalls from E E R OM into hos t interface regis ters are made in groups of either 8 or 16 regis ters . T he choices are programmed into the E E R register in the host interface s ection according to Table 6-3. No jumpers are attached to pins. TABLE 6-4. CONFIG REGISTER/INIT PINS 54 HOST INTERFACE SECTION 83C795 T he recall of LAN addres s regis ters are from the bank selected by the 4-bit E A field and are written to regis ters at I/O locations 08H-0F H, S WH=0. Upon R E S E T, the E A field points to Bank 6. Unless the E E R OM load is bypass ed by jumpers (INIT = 0000), the 83C795 recalls either 8 or 16 regis ters . When Config #6 is jumpered, only 8 registers are recalled and the hardware defaults are us ed for the confi gur ati on r egi s ter s . Al l other i ni ti al configurations res ult in 16 regis ter loads. T hes e are done automatically. S ince E A always initializes to Bank 6, the initial load from the E E R OM always pulls in the LAN addres s from same location. R efer to F igure 6-6 for a depiction of the E E R OM regis ter logic. RESET BANKS OF 8 REGISTERS IN EEROM DISABLE ADAPTER 0 1 2 3 4 GCR2 IAR RAR BIO GCR ERFAL 5 6 7 8 LOAD DEFAULT VALUES INTO REGISTERS LAR0 LAR1 LAR2 LAR3 LAR4 LAR5 BDID CHK 9 ALWAYS TO BANK EA A B C D E F YES BYPASS EEROM LOAD? NO ARE INIT JUMPERS IN POSITION '6'? YES NO UPON RESET, RECALL CONFIGURATION REGISTERS FROM THE BANK ACCORDING TO INIT JUMPERS. (No recall from Bank 6.) RETRIEVE CONFIGURATION REGISTERS PIDL, PIDH, IAR, RAR, BIO, GCR FROM BANK INDEXED BY INIT JUMPERS 0 1 2 GCR2 IAR RAR BIO GCR ERFAL 3 4 5 LAR0 LAR1 LAR2 LAR3 LAR4 LAR5 BDID CHK 6 7 8 9 A B C D E F RETRIEVE LAN ADDRESS REGISTERS FROM BANK INDEXED BY EA FIELD ALWAYS FROM BANK EA (EA powers up at '6') ENABLE ADAPTER NO RECALL? YES RETRIEVE 8 REGISTERS FROM BANK DESIGNATED BY EA FIELD INTO LAN ADDRESS REGISTERS FIGURE 6-6. EEROM REGISTER LOGIC 55 83C795 HOST INTERFACE SECTION 6.7.2.3 Storage Operations T he S tore operation only copies the 8 LAN address regis ters to the E E R OM. T his does not depend upon INIT jumper s ettings . T he s tore operation always moves the LAN Addres s regis ters into the bank s elected by the 4-bit E A field. Table 6-5 defines how each bank of 8 E E R OM locations has been allocated: BANK 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10-1F ALLOCATION USER PROGRAMMABLE ('SOFT') CONFIGURATION CONFIGURATION 1 CONFIGURATION 2 CONFIGURATION 3 CONFIGURATION 4 CONFIGURATION 5 PERMANENT LAN ADDRESS CONFIGURATION 7 CONFIGURATION 8 CONFIGURATION 9 RESERVED FOR DRIVER CONFIGURATION STORAGE CONFIGURATION 11 CONFIGURATION 12 CONFIGURATION 13 CONFIGURATION 14 RESERVED FOR DRIVER CONFIGURATION STORAGE PNP DATA Unlocking the E E R OM F or Write Operations T his convoluted method is used to protect the E E R OM from getting accidentally eras ed by s omeone els e's s oftware. T he E E R OM regis ter (E E R ) looks like this : BIT 7 6 5 4 3 2 1 0 EER WRITE STO RC EA4 UNLOCK EA3 EA2 EA1 EA0 RESET 0 0 0 0 0 1 1 0 T he s cheme requires a s equence of three writes into the E E R OM regis ter to s tart a s tore operation. T he firs t two writes are required to s et the UNLOCK bit and the third write executes the store. T he 1s t write must be: STORE=0, RECALL=0, EA4=X, UNLOCK=0, EA[3-0] = Ch. T he 2nd write mus t be: STORE=0, RECALL=0, EA4=X, UNLOCK=1, EA[3-0] = Ah. T he 3rd write is : STORE=1, RECALL=0, UNLOCK=0, EA[4-0] = EEROM bank. T he value for the E A4-E A0 field is the E E R OM bank you intend to store in it. T he writing of any other value to the E E R other than the required ones in the s equence will s et the locking mechanism back to its initial condition and all three writes will once again be required in s equence to unlock the write protection. Intervening I/O operations to other registers and reads of the E E R OM regis ter do not affect the unlock s equence. TABLE 6-5. EEROM LOCATION ALLOCATION 56 HOST INTERFACE SECTION 83C795 S torage of Us er-Defined Initial Configurations To define any of the 15 recallable configurations , follow thes e s teps. 1. Build an image of the desired configuration registers in the LAN register bank (SWH=0, addr=8:F). Write the unlock/store sequence with the final EA field of the EEROM register selecting the desired configuration bank. Do not use Bank 6 because that is reserved for the permanent device LAN address. Do not use Bank 10 either because that is reserved for driver-related information storage and cannot be recalled as a board configuration. Wait about 200 msec or poll the STORE bit to determine whether that operation has completed. 6.8 PLUG AND PLAY 2. 3. S torage of Us er-Defined LAN Addres s To s tore a us er-defined LAN addres s, follow these s teps. 1. Program the desired LAN address, board ID register, and checksum register with desired values. Write the unlock store sequence with the final EA field of EEROM register selecting the Bank 6. Wait about 200 msec or poll the STORE bit to determine that operation has completed. T he 83C795 s upports the Plug and Play IS A S pecification. T his s pecification provides full and interactive configuration of all PnP -compliant boards ins talled on the IS A bus . T he ess ential s teps in this proces s are the abilities to: * Power up and reset Plug and Play devices * Send out an initiation key to bring all PnP devices into a known state * Isolate each ISA adapter in turn * Read the adapter's resource requirements * Arbitrate the available resources to all of the PnP cards * Identify each board and configure its resources * Activate the cards on the ISA bus * Locate a suitable driver for the adapter, if necessary To be effective in this new environment, the 83C795 contains the logic neces sary to prepare any board on which it is placed for Plug and Play s tandards . T his logic will be active only when both the PNPE N bit (E R FAL.0 as read from E E R OM) is s et and a 3.6k resistor is connectedto the MA[6] pin (JMP6) between MA6 and GND. T his s ection contains a brief overview of how Plug and Play works , along with information s pecific to the 83C795's implementation of PnP. F or more detail on the Plug and Play process and protocol, please refer to the latest vers ion of the Plug and Play IS A S pecification. 6.8.1 Auto-Configuration Ports T he Plug and Play protocol requires that all logic not related to PnP on a PnP board not res pond to any IS A bus acces s until the PnP logicactivates the card, except for devices required for boot (s ee S ection 6.8.5). Until this happens , the only access to the card is through the PnP auto-configurations ports . T hes e ports cons is t of three 8-bit I/O regis ters, as shown in Table 6-6. 2. 3. S torage of Us er-Defined Data In some applications , there may be other data you need to save in the E E R OM, like board type and revis ion numbers , multicas t filter acceptance mas k, s oftware driver parameters , and the host machine type. S ince s ome E E R OM locations may not be needed for configuration or LAN addres s s torage, they can be us ed for this purpos e. Overwrite LAN address, board ID, and checksum registers with the data you need to save. 2. Store the data as if it were a board configuration. The driver setup program uses this method to store driver related parameters into EEROM Bank 10. To recall this us er defined data, program the E A field for the bank and do a R ecall operation. 1. 57 83C795 HOST INTERFACE SECTION Port Name ADDRESS Location Type 6.8.2 Plug And Play States Fixe d a t 0279h Write-only (LPT2 Status Port) T he main Plug and Play s tate machine contains four states and is illustrated in F igure 6-7. All cards will enter the WaitF orK ey s tate in res pons e to either a power-up res et or the R es et and Wait for Key commands . No commands are active in this s tate until the Initiation Key is detected on the IS A bus . T he WaitF orKey s tate is the default s tate for Plug and Play cards during normal sys tem operation. T he Initiation Key places the Plug and Play s tate machine into the S leep s tate. T he Initiation Key cons is ts of a predefined series of writes to the ADDR E S S port. T he write s equence is decoded by on-card logic. If the proper s equence of I/O writes is detected, the Plug and Play auto-configur ation ports are enabled. T he s equence of writes that are expected is : 0x6A,0xB5,0xDA,0xED,0xF6,0xFB,0x7D,0xBE, 0xDF,0x6F,0x37,0x1B,0x0D,0x86,0xC3,0x61, 0xB0,0x58,0x2C,0x16,0x8B,0x45,0xA2,0xD1, 0xE8,0x74,0x3A,0x9D,0xCE,0xE7,0x73,0x39 WRITE_DATA Fixed at 0A79h Write-only (LPT2 Status Port + 0800h) READ_DATA Re lo ca tab le in Read-only ra n g e 0 20 0h - 03FFh TABLE 6-6. AUTO-CONFIGURATION PORTS All writes to the ADDR E S S port are s tored in an address register. T he value in this regis ter is us ed as an index into the internal 256-byte range that holds the P nP configur ation regis ters . Any acces s es to the WR IT E _DAT A or R E AD_DAT A port will be to the PnP configuration regis ter that is currently indexed by the addres s register. S ee s ection 6.8.3 for details on the configuration regis ters. FIGURE 6-7. PLUG AND PLAY STATE MACHINE 58 HOST INTERFACE SECTION 83C795 Any writes to the ADDR E S S port that do not match the Initiation Key sequence will cause the logic to res et back to the s tart of the Key. While the PnP s tate machine is in the WaitForKey state, all access to the R E AD_DAT A or WR IT E _DAT A ports is dis abled. Once the state machine is in the S leep s tate, the board res ponds to a WAKE [CS N] command. E ach PnP board has a regis ter to s tore a Card S elect Number, and this regis ter contains a z ero at power-up. T he card res ponds to a WAKE [CS N] command only if the CS N in the command matches the value in the Card S elect Number regis ter. If the card's CS N does not match the CS N in the WAKE [CS N], it goes into the s leep s tate. T he card s tays in the s leep state until awakened by the correct WAKE [CS N]. If the CS N is zero, then the card enters the Is olation s tate, otherwis e it moves into the Configuration s tate. 6.8.2.1 Isolation A s imple algorithm is us ed to is olate each Plug and Play card. T he is olation protocol requires that each card contain a unique number, referred to as the s erial identifier. T his is a 72-bit number compos ed of two 32-bit fields and an 8-bit checks um. T he firs t field is a vendor identifier. T he s econd can be any value - for example, as erial number or part of aLAN address . T he number is acces s ed s erially, bit by bit, by the isolation logic and is us ed to differentiate the adapters. T he PnP software begins the isolation by s ending out a Wake[0] command. T his will caus e all PnP cards that have not been is olated to trans ition to the Is olation state. If this is the first pas s through the protocol, then the s oftware will pick an initial location for the R E AD_DATA port at this time. T he s oftware then is s ues two reads to the IS OLAT ION regis ter for each bit in the s erial identifier. If the current bit is a '1', then the PnP board is expected to return 0x55 on the first read, and 0xAA on the s econd. If the current bit is a '0', then the PnP logic will drive nothing on the bus , but will ins tead observe the bus to s ee if another card is driving the 0x55, 0xAA pattern. If it does s ee that pattern for the two reads , then that card mus t put its elf back into the S leeps tate. T his ens ures that only one PnP card will be in the Is olation s tate at the end of the protocol. T he PnP s oftware will recognize the 0x55, 0xAA pattern as a '1' for that bit position, and any other pattern as a '0'. Once all 72 bits have been read, the PnP software will then verify that the checks um matches the data. If it does , then the s oftware will as sign a unique, non-zero CS N to the one card that made it to the end of the protocol. T his will cause that one card to trans is tion to the Configuration s tate. If the checks um does not match, then the s oftware will move the location of the R E AD_DAT A port, and s tart the protocol over. 6.8.2.2 Configuration And Activation T he Is olation protocol ens ures that only one card can be in the Configuration s tate at a time. T his makes it poss ible to read out the res ource s tring byte-s erially when in this s tate. T his is done through the R es ource_Data R egister (location 0x04), after polling the status bit (location 0x05, bit 0) to make s ure the data in the regis ter is valid. T he PnP s oftware will us e this method to read the entire res ource s tring from the PnP card. T his s tring lis ts the res ource requirements of the card, along with what the card is capable of us ing (s ee s ection 6.8.5 for more on the res ource s tring). T he s oftware repeats this process with all of the PnP cards in the s ystem, and thus obtains an image of all of the res ource requirements in the sys tem. T he s oftware then arbitrates the available res ources to meet the needs of each card. If a configuration can be found, then the ass igned configuration for each card will be written to the cards . T he s oftware then activates the card by s etting the Activate bit (location 0x30, bit 0). On the 83C795, this caus es the s oftware to trans fer the appropriate s ettings in the P nP confi gur ati on r egi s ter s to the 8 3C79 5's configuration regis ters by way of a s hift chain. Once this transfer is complete, the res t of the logic in the 83C795 becomes active. 6.8.3 Configuration Registers F igure 6-8 contains a map s howing all of the configur ation regis ters implemented by the 83C795. T his figure also illustrates the relationship between the auto-configuration ports , the PnP s econdary addres s s pace, and the res ource string. Mos t of the configuration regis ters can only be acces s ed when the PnP s tate machine is in certain s tates . Any unus ed regis ters or bits in the PnP regis ter s pace mus t return zeros when read. T he 59 83C795 HOST INTERFACE SECTION regis ter map shown in Table 6-7 changes when the adapter is run in I/O-mapped mode (s ee s ection 6.8.6). Als o, when the R OM s pace is dis abled (when BIO.4 and BIO.5 are both s et), the R OM configuration regis ters become read-only and always read zeros . T here are 22-bits of information in the P nP configuration regis ters that are us ed for configuring the 83C795. T hese bits are s hifted from the PnP s ection to the 83C795 section whenever the chip is activated. T he s ame bits are s hifted from the 83C795 s ection back to the PnP s ection at the end of the initial E E R OM load (to get the default values into the PnP regis ters ). S ome of thes e bits may have to be remapped before they are s hifted so as to match the formats of the two different regis ter PNP SECONDARY ADDRESS SPACE Secondary Address 00 01 02 03 04 ISA ADDRESS SPACE 05 06 07 0x0279 0x0A79 0x0200 0x03FF ADDRESS 30 WRITE_DATA 31 READ_DATA 40 41 42 43 44 48 49 4A 4B 4C 60 61 70 71 RAM BASE ADDRESS [23-16] RAM BASE ADDRESS [15-08] RAM CONTROL RAM RANGE LENGTH [23-16] RAM RANGE LENGTH [15-08] ROM BASE ADDRESS [23-16] ROM BASE ADDRESS [15-08] ROM CONTROL ROM RANGE LENGTH [23-16] ROM RANGE LENGTH [15-08] I/O BASE ADDRESS [15-08] I/O BASE ADDRESS [07-00] IRQ NUMBER IRQ TYPE I/O RANGE CHECK ACTIVATE N+1 N+2 Name READ_DATA PORT ADDRESS SERIAL ISOLATION CONFIGURATION CONTROL WAKE (CSN) RESOURCE DATA STATUS CARD SELECT NUMBER (CSN) LOGICAL DEVICE NUMBER Number 0-7 8 9-N EEROM CONTENTS Resource String Item Serial ID Checksum Resource Data Address Function End Tag Checksum FIGURE 6-8. PLUG AND PLAY CONFIGURATION REGISTERS 60 HOST INTERFACE SECTION 83C795 Field Name RAM Base No. 1 2 3 4 5 RAM Size 6 7 PnP Bit 0x40.1 0x40.0 0x41.7 0x41.6 0x41.5 0x44.6 0x44.5 795 Bit PNP Bits RAR.6 RAR.3 RAR.2 RAR.1 RAR.0 RAR.5 RAR.4 6 0 0 1 1 Mapping Function 795 Bits Location Location direct mapping 7 0 1 0 1 RAR.5 RAR.4 1 1 0 0 0 1 1 0 ROM Base 8 9 10 11 12 0x48.1 0x48.0 0x49.7 0x49.6 0x49.5 0x4C.6 0x4C.5 BIO.6 BIO.3 BIO.2 BIO.1 BIO.0 BIO.5 BIO.4 13 0 0 1 1 14 0 1 0 1 BIO.5 1 1 0 0 BIO.4 0 1 1 0 direct mapping ROM Size 13 14 I/O Base 15 16 17 18 0x60.0 0x61.7 0x61.6 0x61.5 0x70.3 0x70.2 0x70.1 0x70.0 IAR.4 IAR.3 IAR.2 IAR.1 GCR.6 GCR.3 GCR.2 19 0 0 0 0 0 1 1 1 1 20 0 0 0 1 1 0 0 0 1 21 0 1 1 0 1 0 1 1 1 22 0 0 1 1 1 1 0 1 1 GCR.6 GCR.3 GCR.2 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 0 1 direct mapping IRQ Level Used 19 20 21 22 TABLE 6-7. PLUG AND PLAY BIT REMAPPING 61 83C795 HOST INTERFACE SECTION s ets . T hes e bits are lis ted in Table 6-7, along with any necess ary mapping information. 6.8.4 Resource String T he Plug and Play res ource s tring is s tored in E E R OM and can be acces s ed either bitwis e through the S erial Is olation regis ter or byte-s erially Byte 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B Value 4D A3 84 16 C0 01 23 45 4C 0A 10 10 82 0D 00 53 4D 43 FF 38 34 31 36 FF 43 61 72 64 Swapped Value B2 C5 21 68 03 80 C4 A2 32 50 08 08 41 30 00 CA B2 C2 FF 1C 2C 8C 6C FF C2 86 4E 26 Name Vendor_ID.0 Vendor_ID.1 Vendor_ID.2 Vendor_ID.3 LAN_Addr.0 LAN_Addr.1 LAN_Addr.2 LAN_Addr.3 Checksum PnP_Version_Type PnP_Version Vendor_Version through the R es ource Data regis ter. T his s tring s hould completely des cribe the res ource needs and options for a 83C795 bas ed card. A s ample version of this structure is lis ted in Table 6-8. Once the 83C795 has been activated by the PnP logic, the res ource s tring is acces s ed in the Description Serial Identifier Plug and Play Version Descriptor ANSI_Identifier_Type Descriptor_Length [7-0] Descriptor_Length [15-8] ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Character ANSI Descriptor for Card -S -M -C - -8 -4 -1 -6 - -C -a -r -d TABLE 6-8. PLUG AND PLAY RESOURCE STRING STRUCTURE 62 HOST INTERFACE SECTION 83C795 Byte Value Swapped Value 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 15 4D A3 84 16 02 23 A8 8E 16 47 00 00 02 E0 03 20 20 81 09 00 11 00 0C E0 0F 00 40 40 00 79 0E A8 B2 C5 21 68 40 C4 15 71 68 E2 00 00 40 07 C0 04 04 18 90 00 88 00 30 07 F0 00 02 02 00 9E 70 Name Logical_Device_Type Logical_Device_ID.0 Logical_Device_ID.1 Logical_Device_ID.2 Logical_Device_ID.3 Logical_Device_Flags Interrupt_Descriptor_Type IRQ_Mask [7-0] IRQ_Mask [15-8] IRQ_Information I/O_Port_Descriptor_Type I/O_Port_Info I/O_Min_Base_Addr [7-0] I/O_Min_Base_Addr [15-8] I/O_Max_Base_Addr [7-0] I/O_Max_Base_Addr [15-8] I/O_Base_Alignment I/O_Range_Length Description Logical Device Descriptor (Non-boot, does I/O range checking) Interrupt Format Descriptor - Interrupts supported: 3, 5, 7 - Interrupts supported: 9, 10, 11, 15 I/O Port Descriptor - Minimum Base Address = 0x0200 - Maximum Base Address = 0x03E0 - Alignment = 32-byte blocks - Length = 32 bytes Memory_Range_Descriptor_Type Memory Range Descriptor #1 Descriptor_Length [7-0] (two would be required for cards using Descriptor_Length [15-8] Memory_Range_Information Mem1_Min_Base_Addr [15-8] Mem1_Min_Base_Addr [23-16] Mem1_Max_Base_Addr [15-8] Mem1_Max_Base_Addr [23-16] Mem1_Base_Alignment [7-0] Mem1_Base_Alignment [15-8] Mem1_Range_Length [7-0] Mem1_Range_Length [15-8] End_Tag_Type Checksum - Length = 16 kbytes End Tag - Covers all data bytes - Maximum Base Address = 0x0FE000 - Alignment = 16-kbyte blocks - Minimum Base Address = 0x0C0000 both ROM and shared RAM) - 8-/16-bit, writable TABLE 6-8. PLUG AND PLAY RESOURCE STRING STRUCTURE (cont.) 63 83C795 HOST INTERFACE SECTION s ame manner (for both reads andwrites ) as the res t of the E E R OM contents, except that E A[4] (E E R .5) mus t be s et. 6.8.5 Configuring As A Boot Card 6.9 EXTERNAL POWER SUPPLY CONTROL Many LAN adapters are configured as boot cards . S ince thes e cards must be vis ible to the BIOS at boot time, they may have to be activated before the PnP s oftware has had a chance to run. T he PNPBOOT bit (IAR .0) was implemented to do this . When this bit is read out of E E R OM as s et, the chip becomes active on the IS A bus . T his bit als o forces bit 0 of the IAR regis ter to '1' which identifies the card as a boot card to the PnP s oftware. 6.8.6 Configuring With An I/O-Mapped Pipe T he GPOUT pin can be used to control an external power s upply s upporting a 10Bas e2 MAU circuit. T his pin can be used to s ource either a simple DC control s ignal or a puls e train. T he DC s ignal is us ed to enable or dis able a controllable power supply. Note The DC signal's polarity on the 83C795 is the opposite of the 83C790's. T he puls e train is designed to be the switching control signal for a s pecific design of switching power s upply. T he puls e train includes a start-up s equence as well as a choice of two normal operating pulse trains . Before the GPOUT pin can emit a puls e train, ins tall the INIT 5 jumper to pull down the MA5 pin. T he INIT 4 jumper determines which of the two pulse trains is emitted. T he puls e train is turned on or off us ing the GCR .GPOUT bit (s ee page 21 for details). T he puls e train is a 312 KHz signal with 1/8 duty cycle for the firs t 1024 clocks after GPOUT is enabled. T his is followed by 1/4 duty cycle for 1K clocks , 3/8 duty cycle for 1K clocks , and 1/2 (50% ) duty cycle thereafter. Ins tallation of the INIT 4 jumper caus es the final duty cycle to be 17/32 (53% ) ins tead of 1/2. When the 8 3 C7 95 i s confi gur ed wi th an I/O-mapped pipe ins tead of s hared memory, the board will not use any memory addres s s pace for the buffer R AM. T herefore, the PnP R AM control regis ters (us ually locations 40h-44h) are not neces s ary. If this card requires a R OM, then the descriptor for the R OM memory window will be the firs t one in the res ource s tring. T his requires that the PnP R OM control registers be re-mapped from 48h-4Ch to 40h-44h. T his is accomplis hed by s etting the PNPIOP bit (GCR 2.0). T his bit mus t be read out of E E R OM because it must have the correct value before the chipis activatedby the PnP logic. S etting this bit als o caus es locations 48h-4Ch to read as zeroes . 6.8.7 Buffer Memory Limitations Normally, buffer memory can be located above the 1MB DOS limit by s etting the buffer addres s line (LA23-LA20) decoder to match at 'F' rather than zero (done by s etting the HR AM bit, R AR .7). T his is not s upported by the P nP hardware as implemented in the 83C795. 64 LAN CONTROLLER OVERVIEW 83C795 7.0 LAN CONTROLLER OVERVIEW T he LAN Controller cons is ts of 3 bas ic blocks : DMA controller, transmitter, and receiver. E ach of thes e blocks cons is ts of s ub-s ections . T he DMA controller includes a memory interface unit, control regis ters , and a micro-coded s equencer that handles data buffering for the trans mitter and receiver s ections. T he trans mitter block has a MAC (Media Access Control) s ection that performs the IE E E 802.3 trans mis s ion protocol and a P hys ical L ayer Interface (P L I) s ection that does Manches ter encoding and drives the cables. T he receiver block has aMAC s ection that performs the 802.3 reception protocol and a PLI s ection that converts line level differential signals to internal logic s ignals while doing clock recovery, and manches ter decoding. 7.1 DMA CONTROLLER T he DMA controller handles data movement between the F I F Os and buffer memory for trans miss ion and reception of frames . All DMA data traffic is 8-bit wide. One DMA controller is s hared between the trans mit and receive functions . T he controller groups memory trans fers into burs ts of 8 bytes for both transmit and receive functions . T he DMA controller always access es memory by doing two s ingle-byte trans fers in a row. T he burst size and its trigger levels are s hown in Table 7-1. BURST R 8 TRIGGER LEVEL RX TX T 8 T hough internally 8 bits wide, the DMA controller generates 16-bit addres s es . It acces ses memory in 2 cycles of the chip's mas ter clock (per byte). When conducting a loop-back tes t, this controller can handle full-duplex buffering of full length frames at serial datarates upto 10 Mbps . It does not handle the general cas e of independent (concurrent) trans mit and reception proces ses . 7.1.1 Assembly and Disassembly Latches T hes e latches are us ed to match up the internal 8-bit data path with the external data bus . As sembly latches build a 16-bit word out of two 8-bit words or s upplies the consecutive bytes when interfacing to an 8-bit bus . Dis as s embly latches perform the invers e function. T hes e are us ed during DMA operations and are bypas s ed when the chip's regis ters are written or read. 7.1.2 Memory Interface Unit T he memory interface unit (MIU) transfers data from buffer memory to the internal dis as sembly latches and from the internal ass embly latches to buffer memory. It is a part of the DMA controller. T his block generates the memory s tr obes (R AMOE , R AMWR ) when the DMA is acces sing the buffer R AM. MIU operation is initiated by the DMA controller after it sets up the address for the trans fer and puts outgoing data (receiver functions ) into the as s embly latches . T he MIU then performs the memory trans fer in the next time s lot as s igned to the DMA. T he bas ic DMA cycles are in F igure 7-1. R eal details can be found in the AC timing s ection. 8 bytes TABLE 7-1. DMA BURST LENGTH FIELD 65 83C795 LAN CONTROLLER OVERVIEW CLK STATE 0 0 1 1 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 1 1 1 1 1 DMASEL ADDRESS DATA CACHE CACHE EVEN EVEN+1 CACHE CACHE EVEN+2 LOW EVEN+3 CACHE CACHE LOW HIGH HIGH RAMWR DMA WRITES CLK STATE 0 0 5 5 6 7 8 5 5 5 5 5 5 5 5 5 5 5 5 5 6 7 8 5 5 5 5 DMASEL ADDRESS DATA CACHE CACHE EVEN EVEN+1 CACHE CACHE EVEN+2 LOW EVEN+3 CACHE CACHE LOW HIGH HIGH RAMOE DMA READS FIGURE 7-1. BASIC DMA CYCLES 66 LAN CONTROLLER OVERVIEW 83C795 7.1.3 LAN Controller Internal Bus Arbitration T his portion of the 83C795 is us ed to res olve conflicts that can occur on data bus es us ed by both the DMA controller and hos t acces s es to the internal regis ters of the LAN Controller s ection. T he LAN bus arbitration s ection obs erves a LAN s elect (CS ) signal derived from the memory bus arbiter and provides a 'ready' hands hake s ignal in return. It als o controls internal data flow within the L AN contr ol l er and hol ds off the DMA microcontroller during I/O acces s es . 7.1.4 DMA Microcontroller T he core of the DMA controller is a R OM-bas ed microcontroller which includes an addres s counter for the memory pos ition, comparators for internal address comparis ons , s ome decrementers for loop control, regis ters for s torage of operating variables , and I/O control s ignals that attach to many circuits within the LAN controller s ection of the chip. In addition to the microcode as s ociated with normal trans mit, receive and loopback proces ses , there is additional code to facilitate tes ting of the LAN controller. 7.1.5 How to Access Registers A request for LAN regis ter acces s is made when the host presents an I/O addres s that decodes to a regis ter within the upper 16 bytes of the 83C795's I/O block and a valid IOR or IOW is pres ented. T he chip will res pond with an I/O Channel Not R eady s ignal (IOR DY) while internal arbitration proceeds . It remains NOT IOR DY until the des ired trans fer is ready to be completed. Acces s to the regis ters of the LAN controller s ection is allowed after any ongoing DMA bur s t is completed. At that time, the DMA may wis h to become active again in res pons e to new needs , but the arbitration logicwill allow hos t acces s to the chip until the I/O strobe becomes fals e. T he arbiter generates the IOR DY s ignal as an indication to the host that the internal bus has been made available and that the reques ted I/O access has been made. Between acces s es to the chip, IOR DY is undriven. To read from a register, an I/O addres s is placed on the S Axx pins andIOR is ass erted by the hos t (mus t be as s erted after a valid addres s ) and recognized by the bus arbitration logic which enables data flow from the address ed regis ter to the D00-D07 pins . R egis ter reads are always done through the D00-D07 pins , except for 16-bit I/O pipe acces ses . T he D08-D15 pins will be tri-stated during read operations. IOR DY will indicate when the hos t may s ample data and terminate the read operation. To write to a register, an I/O addres s is placed on the S Axx pins and IOW is ass erted by the hos t and recogniz ed by the bus arbiter. Addres s mus t become s table before IOW is as serted. When the bus is free for the trans fer, IOR DY is as s erted. Data is latched into an intermediate trans fer latch with the trailing edge of IOW and then trans ferred to the destination regis ter two clocks later. T his delayed write operation requires an internal recovery period between hos t acces s es to regis ters. T his period is documented in the detailed timing diagrams . 7.1.6 Memory Interface T he internal DMA controller moves packets between buffer memory and the F IF Os . 67 83C795 LAN CONTROLLER OVERVIEW 7.2 FIFOS 7.3 T here are two F IF O s tructures us ed to expedite the trans fer proces s between the DMA process or and the T rans mit/R eceive units. E ach F IF O is 16-bytes deep. As s ociated with each F IF O are up/down counters that keep track of how full each F IF O is . T he normal loading s ource for each F IF O receives an overflow indication when it occurs and the normal unloading des tination has an empty signal to prevent drawing of nonexis tent data. RECEIVER NETWORK INTERFACE (PHY-TO-MAC) T his s ection of the 83C795 has s quelched, differential receivers for the AU I and T WP interfaces . T he inputs from thes e interfaces are multiplexed together with a feedback path to a common phas e-locked-loop circuit for clock recovery and data decoding. F igure 7-2 s hows the AUI and T wis ted-Pair interface relations hip. FIGURE 7-2. AUI/TWISTED-PAIR INTERFACE 68 LAN CONTROLLER OVERVIEW 83C795 7.3.1 AUI Differential Receiver With the standard 78 transceiver AUI cable, the differential input must be externally terminated. T his requirement may be satisfied by connecting two 39 resistors in series with one optional common mode bypass capacitor. To prevent nois e at the AUI R X+/- input from falsely triggering the decoder, a s quelch circuit rejects s ignals with puls e widths les s than 25 ns ec (negative going), or with levels les s than 175 mV. When the input exceeds the s quelch levels , the analog phas e-locked loop locks into the incoming s ignal and Manches ter decoding takes place. T he internal carrier sens e s ignal is activated and the receive data (R XD) and the receive clock (R XC) become available within s even bit times . At the end of a frame when normal mid-bit trans ition on the di fferential input ceas es , carr ier s ens e is deactivated. T he receive clock remains active for an additional 5 bit times. 7.3.2 Twisted-Pair Differential Receiver T he received s ignal from the unshielded cable may be nois y, s o minimum voltage and timing limits mus t be met before the receiver logic is enabled. A 'S mart S quelch' digital nois e filter is us edin addition to the analog squelch circuit in the receiver. I f the input polarity is r ever s ed i t wi ll be automatically detected and corrected. When polarity is normal, the PLE D (MANCH.3) bit will be s et. T he phas e-locked loop and Manches ter decoder are the s ame circuits us ed by the AUI receiver. 7.3.2.1 Extended Length For Twisted-Pair S etting the XLE NGT H bit (GCR .7) increases the s quelch levels us ed by the T P receiver. T his enables the adapter to be connected to a cable that is longer than s pecified by the 802.3 s tandard. 7.3.3 Manchester Decoder Decodi ng i s accompl i s hed by an anal og phas e-l ock ed l oop that s epar ates the Manches ter-encoded data s tream into clock s ignals and NR Z data. T his loop can tolerate up to 20 ns ec of jitter on each s ignal edge, exceeding the 802.3 requirements . 7.3.4 Carrier Sense T he AUI interface determines carrier presence by requiring the differential received s ignal to exceed the negative s quelch level for a minimal period, nominally 25 ns ec. T he twis ted-pair interface requires that the pos itive and negative s quelch levels be exceeded s everal times for a period of at leas t 20 nsec. When operating in loopback mode, internal transmit enable s ignal is returned to the MAC as the carrier indication. 7.3.5 Collision Detect Collision detection for the AUI interface is indicated when the differential s ignal on the CD input pair exceeds the negative squelch thres hold. Collision detection for the twis ted-pair interface is indicated when there is carrier s ensed while the trans mitter is active. 7.3.6 Loopback Mode When the LAN controller is programmed to operate in loopback mode 2, it provides a s ignal to the line receiver s ection which caus es the Manches ter decoder to derive its input from the encoded trans mit data ins tead of the differential receivers of AUI and T P interfaces. T he AUI and T P interfaces are ignored while the loopback indication is active. 69 83C795 LAN CONTROLLER OVERVIEW 7.4 7.4.1 MAC RECEIVER Basic Functions T he 83C795's receiver section process es a s erial s tream of NR Z data. T he s tart of the frame is identified, des tination addres s is checked agains t the s tation addres s , recogniz ed fr ames are trans ferred to memory and checked for valid formation. E rror conditions are reported. 7.4.2 Interface to the MAC Receiver T he s erial interface to the MAC receiver s ection is handled by four signals : Carrier S ens e (XCR S ), Collision Detect (XCOL), R eceive Data (XR XD), and R eceive Clock (XR XC). T he group may come from one of three s ources : * internally from the Manchester Decoder * direct from the pins * internally from the transmit section. All sources are treated equally. S election of s ource is done by programming configuration regis ters . R efer to the T CON and MANDIS R egis ters for further information. Note These signals are multiplexed with the IRQ pins and are used for testing purposes only. 7.4.3 Loopback Paths T he 83C795 has 3 loopback modes . Mode 1 provides the path between receiver and trans mitter ins ide the LAN controller. In this mode, NR Z data from the trans mitter connects to the receiver's R X D input, bypas s ing Manches ter encoder/decoder. XR XC is generated internally for this mode by dividing 20 Mhz clock by two. T he minimum frame length for mode 1 loopback is 25 bytes. Mode 2 connects trans mit and receive data through the Manches ter encoder/decoder. T he s erial data is wrapped around jus t inside the device pins with neither AUI nor T P interfaces actually driving the outs ide world. T he minimum frame length for mode 2 loopback is 25 bytes . Mode 3 has trans mitter and receiver pins active with loopback pins inactive. T he DMA controller will run its s pecial loopback code to allow reception of the outgoing trans miss ion if it is echoedback. In this mode, the DMA can handle delay of the echo provided that the frame's length exceeds echo delay by at leas t 200 bit times (25 bytes ). When run in this mode, the board being tes ted should be connected to an 802.3-compliant cable. T hat cable may or may not have other 802.3 nodes attached. Note Caution is advised when running this test on a live network or when other nodes on the test cable could send a frame to the node under test. Reception of a frame destined to the loopback node could confuse the results of the loopback test as the node will be able to receive the incoming frame. 7.4.4 Receive Deserialization R eceive des erializer is activated by carrier s ens e. Byte alignment is determined by a synch circuit which detects the S tart-of-F rame Delimiter (S F D) when it s ees the serial s equence '10101011' after the start of carrier s ens e. T his pattern marks the firs t octet boundary and determines byte alignment for the entire frame. Incoming R XD bits are clocked into an 8 bit wide s erial-to-parallel s hift regis ter. T he bits are received in order from leas t s ignificant to mos t s ignificant within each byte. When an octet is complete, parallel data is loaded into the receiver F IF O. When Carrier is los t, the frame is considered to have terminated; and all remaining s erial data are dropped. S erial data is pas s ed to the CR C checker which is initialized upon recognition of the S F D. T his proces s ordinarily dis cards all bits that precede the S F D pattern without prejudicing reception of the frame. S ome exceptions can be made to this proces s to improve the robustnes s of the receiver. T hey are dis cus s ed below. T here is a s electable mode (us ing the R CON.R CA bit) during the receiver operation which adds robus tnes s by monitoring the X COL s ignal continuous ly throughout reception, s tarting after the S tart-of-F rame delimiter. If collision is detected, reception of the frame is aborted. 70 LAN CONTROLLER OVERVIEW 83C795 Operating in ALT E GO mode engages a second improvement to the reception proces s . T he receiver checks for corruption of the preamble and terminates reception of any frame which has cons ecutive '0' bits . All valid preambles have an al ter nati ng '1 0 ' patter n fol l owed by the S tart-of-F rame delimiter ('11'). T he above is checked immediately on the as s ertion of the internal carrier s ens e without any grace periods . Neither of thes e causes for abort forces logic to s et R XE . 7.4.5 CRC Checker If reception of multicas t frames has been enabled and if the 6-bit partial CR C points to a bit in the table that has been turned on, the multicas t frame will be recognized. Broadcas t frames are received when the Broadcast E nable bit (R CON.BR OAD) is active or when the hashed bit in the Multicast F ilter table has been s et. To caus e promiscuous reception of multicas t and broadcas t frames , the entire Group Addres s table s hould be turned on and reception of multicas t frames enabled. If the addres s is rejected, the frame is als o rejected and none of the frame is trans ported to the buffer memory. If the addres s is recognized, buffering of the frame begins . 7.4.7 Received Byte Counter and Early Receive Warning Interrupt T he R eceiver computes the CR C of an incoming frame serially. CR C computation includes addres s , data, and CR C frame fields . It excludes preamble and S F D. Computation s tops after reception of las t whole octet following los s of carrier. T he final value of the CR C mus t be "C704DD7B" for the packet to be validated. T he CR C polynomial us ed is AUT ODIN II: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1. If the received frame's CR C does not check out, a CR C error is indicated in the S tatus R egister and the CR C E rror Counter is incremented. F rame r ecepti on wi l l ter mi nate unl es s the R eceive-with-E rrors mode is enabled. In addition, if the number of bits received in the las t octet (when the carrier is terminated) is greater than one and les s than 8 (a full octet), and the CR C check for all complete octets fails , the frame is als o labeled as an 'alignment error' and an error flag is s et in the S tatus R egis ter; if this occurs , the Alignment E rror Counter will be incremented. 7.4.6 Address Recognition Logic T his circuit counts the number of bytes in each completed frame and filters out runt frames (less than 64 bytes) unles s the runt filter is defeated by s etting the Accept R unt bit in the R eceive Configuration R egis ter (R CON.R UNT S ). T he E arly R eceive Warning (E R W) interrupt is generated when the received byte count equals or exceeds a value specified in the E arly R eceive Warning Count R egis ter (E R WCNT ). T he value of E R WCNT is left-s hifted four bits (multiplied by 16) before it is compared to the receive byte count. T he value is 8 bits wide, allowing the E R W thres hold to be s et between 0 and 4K with a res olution of 16 bytes. T he E R W interrupt is only generated if an active reception is in progres s. Once an early receive interrupt has been set, it may be cleared and will not be s et again until another packet exceeds the E R W thres hold or the E R WCNT R egis ter is written to. Writing a value to E RWCNT that is les s than the current receive byte count (while reception is in progres s ) will automatically s et the E R W interrupt. T he E R W interrupt is mapped to bit 6 in the Interrupt S tatus R egis ter (INS T AT ). T he E RW interrupt is enabled or disabled like all other interrupts by the corres ponding bit in the Interrupt Mas k R egis ter (INT MAS K). Des tination addres s es that are 'individual' are compared to a 6-byte s tation addres s s tored in regis ters. If all bits match or if the PR OMIS CUOUS mode is enabled, the frame is received. A snapshot is taken of the partially-computed CR C as the end of the des tination field pas s es through the CR C checker. If the addres s has the 'group' or 'multicast' bit s et, 6 bits of this checks um are us ed as a has hed index to a 64-bit Multicas t F ilter table. 71 83C795 LAN CONTROLLER OVERVIEW 7.4.7.1 Early Receive Failure Detection During the reception of a frame with early receive enabled, it is pos s ible for the hos t to readframe data from the buffer R AM before the DMA writes it if the early receive thres hold is set too low. T he failure detection logic enables the hos t to detect if this has happened; if s o, it goes back and recopies the correct data. T he logicrequired for this is similar to the logicus ed for early transmit underrun detection. T he local memory addres s is latched every time the DMA writes to the buffer R AM. When the memory cache or I/O pipe reads data from the R AM, the local memory addres s is compared to the las t latched addres s . (T he leas t s ignificant 2 bits are not compared s o the detection mechanis m has a granularity of 4 bytes ). T his comparison is turned off when the DMA finishes placing the frame in s hared memory. If the two address es are equal, E R F BIT (UBR CV.1) is s et and the latched address is s tored in the E R FA regis ters (E R FAL and E R FAH). When the host reads that E R F BIT is s et, it should begin recopying data from a point at or before E R FA and res et E R F BIT. Note The value in ERFA contains the local memory address where the failure occurred, not the host address. T he E R FA regis ters remain s et until the host clears the E R F BIT. F or more on E R F BIT, s ee page 40. F or more on the E R FA registers , s ee page 22. 7.4.8 Receive Protocol FSM T he R eceive Protocol F S M interfaces with the DMA s ection to coordinate buffering of received frames . It informs the DMA of abort conditions, s hould they occur as well as valid completions of received frames . After the frame has been buffered to memory by the DMA, the DMA s ection copies the R eceiver S tatus R egis ter (R S T AT ) and the number of bytes received from the receiver into the header of the buffer. T he receiver F IF O is monitored for overflow conditions and if one occurs, frame reception is terminated and an error flag is pos ted to the S tatus R egis ter. T he R eceiver s ection is enabled by s etting the S tart and clearing the S top bits in the Command R egis ter - CMD.S T A and CMD.S T P. Until enabled, the receiver s ection ignores incoming frames . Once the S tart bit has been s et, it remains true internally until the S top bit is set or the chip is res et. Clearing the S tart bit in Command R egis ter does not caus e the receiver s ection to s top operating. If the S top bit is s et while receiver is operational, it will complete the handling of any ongoing frame and then go to a s oft res et condition, ignoring new incoming frames . T he receiver will clear the R S T AT R egis ter when the current frame is finis hed and pos ted. When both trans mitter and receiver s ections are s topped, the R S T bit in the interrupt s tatus regis ter will be s et. It s hould be notedthat the DMA controller may remain active while S top is s et. T he protocol machine can be configured to operate in a "Monitor Mode" which checks validity of incoming frames and maintains error s tatis tics for them but does not store them in memory. E ach time an acceptable frame is completed while in this mode, the Mis s ed Packet Counter (MPCNT ) is incremented. T his counter is not incremented by F IF O overflows . 7.4.9 Reception Process T he R eceive Protocol F S M controls reception of frames, checks for errors , and posts s tatus to a regis ter after completion of each reception. It operates counters for the number of bytes in the frame and for three types of error conditions . T he receiver protocol F S M can be configured via a regis ter, allowing some flexibility as to which frames are to be received. T he receivedbyte counter is 16-bits wide. T he three error counters are each 8-bits wide. T hes e will count from zero up to 255, where they s tick to avoid wrap-around. T he error counters are s elf-clearing when readandthey can generate a sharedinterrupt condition when any of them have countedupto 192. IE E E 802.3 packets consist of thes e fields and are therefore proces s ed in this order: * Preamble field * SFD field * DA field * SA field 72 LAN CONTROLLER OVERVIEW 83C795 * Data field * CRC field E ach of these fields is explained in the following s ections . 7.4.9.1 Start of Frame T he preamble field is us ed to train the Manches ter decoder and to detect carrier. If carrier is detected, preamble pas s es through the receive deserializer whi ch di s car ds i t whil e s ear chi ng for the S tart-of-F rame Delimiter (S F D) s ymbol. On detecting a good S F D, a VALID_F R AME s ignal is as serted and the receive F IF O is cleared to accept the received frame. T he receive F IF O is loaded by the des erializer with octets (bytes ) s tarting with the firs t bit after S FD. While the destination addres s (DA field) is being checked for recognition, the receive DMA is dis abled. If the addres s is recognized, the DMA is enabled and trans fer to memory begins when the F IF O fills to the programmed burs t level. If the frame's addres s is not recognized, the receive unit clears out the F IF O, s tops filling it, and waits for the s tart of the next frame. T he s ource addres s and data fields are pas sed to buffer memory. In some protocols , the firs t 2 bytes of the data field denote a frame length. T hes e bytes are not interpreted by the S MC795. T hey are treated as ordinary data. 7.4.9.2 End of Frame If there is a los s of carrier s ense, 3 dribble clocks (receive clocks that occur after the los s of carrier s ens e) are needed to ens ure the s ynchronizations of all line s ignals to the receiver circuits . When using the internal Manchester decoder (either 10BAS E -T or AUI interfaces ), this decoder automatically s upplies s ufficient dribble clocks to the receiver to complete proces s ing of the frame. When the Manches ter decoder is bypass ed, it is neces s ary to s upply dribble clocks at the XR XC pin after XCR S terminates. T he CR C from the received frame is s ent to memory with the frame via DMA and is included in the byte count pos ted in the buffer header. If the receive unit detects errors in the frame (s uch as an incorrect CR C, an alignment problem, a fores hortened frame), it can abort reception depending on the configuration of the S ave E rrored Packets and Accept R unt F rames bits of the R eceive Configuration R egis ter - R CON.S E P and R CON.R UNT S res pectively. Certain other types of errors (including FIFO overflow andR eceiver Buffer Overwrite) always abort reception. If reception is aborted, the DMA controller s tops s ending bytes to the buffer, the R eceive S tatus R egis ter (R S R ) and the Interrupt S tatus R egis ter (IS R ) are updated, and the receive unit waits for the next frame to begin. No buffer header will be pos ted for the frames that have not been accepted; the previous contents of the header location will remain unchanged. T he received packet length s hould be les s than 32,764 bytes , including DA, S A, data, and CR C. T he receiver does not reject longer frames but it may be hard to fit the contents into available buffer s pace. T he buffer ring mus t always have enough s pace to contain the entire frame with a 4-byte header. Packets larger than the available buffer s pace will not be received, regardles s of the S E P bit in the R CON R egis ter. S uch frames will be posted as ring overwrites and caus es the OVW interrupt to be s et. R eceiver interrupts (R XE for frames with errors and PR X for frames without errors ) indicate the DMA has completely pos ted the frame to memory. If the DMA aborts , thes e interrupts are not set for the current frame. If s et previous ly, they remain unchanged. Packets s horter than 64 bytes will be r eceived only when the Accept R unts bit (R CON.R UNT S ) is enabled. 7.4.10 Receiver Blinding T he R eceiver Carrier S ens e function is blinded for a period of 4.0 s ec starting at the end of (XCR S + XCOL) when the device has trans mitted a frame. T his allows the heartbeat to be detected without res etting the deference timer and ens ures that an improperly-s paced frame will not interfere with proper pos ting of s tatus for a new reception. 73 83C795 LAN CONTROLLER OVERVIEW 7.5 TRANSMITTER NETWORK INTERFACE (MAC-TO-PHY) Oscillator 7.5.4 Collision Translator 7.5.1 A 20 Mhz parallel res onant crys tal can be connected between pins X1 and X2; or an external clock can be connected at X1. T he oscillator's 20 Mhz output is divided in half internally to provide the clock s ignals for the encoding and decoding circuits. Operation at s erial data rates other than 10 MHz requires an externally-s uppliedclock since the os cillator is only tuned for 20 MHz. T he IE E E 802.3 s tandard requires 0.01% abs olute accuracy on the trans mitted s ignal frequency; however, s tray capacitance can s hift the crys tal's frequency out of range caus ing it to exceed the 0.01 tolerance. 7.5.2 Manchester Encoder When the 83C795 is us ed as an AUI device, a s eparate E thernet trans ceiver (MAU) detects collis ions on the coaxial cable and generates a 10 Mhz s ignal which is monitored by the 83C795 through the collis ion detect pins (CD+, CD-). T he pres ence of this s ignal activates the internal collis ion detect s ignal (CD) connected to the LAN controller. T he collis ion detect s ignal is deactivated within 160 ns ec after the abs ence of the 10 Mhz s ignal. With the s tandard 78 trans ceiver AUI cable, the CD+/CD- differential input pair mus t be externally terminated. T his requirement may be s atis fied by connecting two 39 res is tors in s eries with one optional common mode bypas s capacitor. When 83C795 is us ed in twis ted-pair configuration, the collis ion is generatedif the Manches ter decoder detects carrier while the trans mit enable is active. 7.5.5 Twisted-Pair Differential Driver Data encoding and trans mis s ion begin when the internal trans mit enable s ignal from the L AN controller goes high and continues as long as it remains high. T rans mis s ion ends when the T ransmit E nable s ignal goes low. T he last trans ition occurs at the center of the bit cell if the las t bit is '1' or at the boundary of the bit cell if the last bit is '0'. 7.5.3 AUI Differential Driver T he AUI differential line driver has the ability to drive up to 50 meters of twis ted-pair AUI/E thernet tr ans cei ver cabl e. T hes e dr iver s pr ovi de emitter-coupled logic (E CL) level s ignals . T he outputs cons is t of current drivers that mus t be loaded with external 150 pull-up resistors . T he interface can be programmed to operate in either half-step or full-s tep mode in the idle state. T his is done via the S E L bit in the MANCH R egis ter. In full-s tep mode, T X+ is positive in relation to T Xwhen idle. In half-step mode, T X+ and T X- are equal, res ulting in nearly zero differential output voltage. By setting a bit in the MANCH R egister, Manches ter encoder /decoder l ogi c can be bypas s ed completely. E xternal circuitry s hould drive XT XC, XR XC, XCR S , XR XD, and XCOL pins. T he T P Driver can trans mit through up to 100 meters of uns hielded twis ted pair cable. T he driver includes a circuit for trans mit equalization which attenuates the trans mit waveform's low-frequency components . T his reduces the received signal's zero-cros s ing jitter and makes the receiver design s impler. In the trans mitter, phas e compens ation is us ed to reduce jitter. T his is accomplis hedby us ing external res is tors to determine the drive s trength during the s econd half of a double-width puls e as compared to the drive s trength of the firs t half. T here are two pairs of twis ted-pair trans mit drivers : T PX1 and T PX2. T PX2 is a much weaker driver than T PX1. During the firs t half-bit-time of each puls e, both pairs of drivers drive out the encoded trans mit data. If the pulse is afull-bit-time in length, T PX2 s witches polarity during the s econd half of the puls e and acts to reduce the amplitude of the trans mitted s ignal. A s implified example of external trans mit circuitry is s hown in F igure 7-3. 74 LAN CONTROLLER OVERVIEW 83C795 7.5.6 Link Integrity Test Function 7.5.7 Jabber Protection E ach T P driver transmits a s hort pos itive pulse periodically when it is not s ending data. T hese puls es are received at the other end of the twisted pair cable, s ignaling that the link is operating correctly. T he time between link tes t puls es is compared to the expected range at the receiver to help ignore nois e pulses . If the link tes t fails (no puls es or data received within a fixed time period) then the LLE D pin is set high and AUI interface is s el ected. I f the li nk i s r es tor ed, the chip automatically s elects T P interface. T he Link Integrity Tes t is als o us ed to correct the receiver connection's polarity. T he Link Integrity Tes t s ignal and S tart-of-Idle both have pos itive polarity. T he polarity correction s tate machine looks at both of thes e to determine whether to flipreceiver polarity. Polarity correction can be dis abled by a bit in the MANCH R egister (MANCH.E NAPOL). T he Link Integrity Tes t can be disabled by a bit in the General Control R egis ter (GCR .LIT ). Dis abling L ink T es t forces the 83C795 to s elect the twisted-pair interface. If the internal trans mit enable s ignal is active for more than 46 ms ec, the twis ted-pair trans mitter will be dis abled and a collis ion indication is s ent to the MAC trans mitter circuit. When the internal transmit enable s ignal has been inactive for more than 368 ms ec, the internal collis ion indicator will become inactive and the twis ted-pair trans mitter will be re-enabled. Jabber protection for the AUI port is provided by an external MAU. 7.5.8 SQE Test (Heartbeat Test) In twis ted-pair operation, a brief internal collision indication will be sent to the MAC trans mitter after each packet is trans mitted. When an AUI port is in us e, an external MAU will provide this s ignal. 7.5.9 Status Indications To as s is t in ins tallation and management of the network, indicator LE Ds can be driven directly by four outputs from the 83C795. T hes e s how the res ult of Link Test, polarity check, trans mit and receive activity. T he LE D outputs can be read back through the MANCH regis ter to s upport network management functions . TPX2+ TPX1+ R34 R31 60 60 R32 240 83C795 TPX1TPX2R33 240 20 MHz Low Pass Elliptic Filter 100 Ohms Phone Jack R31 || R32 = 50 Ohm = R33 || R34 Ratio of R31 to R32 determines how much smaller the second half of the pulse is than the first half Polarity TPX1 TPX2 + + - + + + - - + + - + + + + - - + + + 1 1 0 0 1 0 1 FIGURE 7-3. SIMPLIFIED TRANSMIT CIRCUITRY 75 83C795 LAN CONTROLLER OVERVIEW 7.6 7.6.1 TRANSMITTER SECTION Basic Function 7.6.5 Transmit Protocol FSM T he trans mitter section generates s erial stream of NR Z data. It produces preamble and the S F D field at the beginning of aframe, then data is s hiftedfrom the F IF O serially followed by the CR C field. T he trans mitter checks for collisions and retrans mits the frames if neces s ary, it counts interframe gap and implements random backoff algorithm. It maintains the trans mit s tatis tics and generates s tatus information on each attempted trans mis s ion. S election of optional operating modes of the T r ans mi tter s ecti on i s done pr i mar i l y by programming the T rans mit Configuration regis ter. 7.6.2 Preamble Generator At the beginning of each frame, the trans mitter generates 56 bits of preamble (an alternating '1010' pattern). Immediately after this , it generates a S tart F rame Delimiter s equence which is '10101011.' 7.6.3 Transmit Serializer T he T rans mit S erializer converts 8 bits of parallel data from the F IF O into s erial transmit NR Z data. Data is s hifted out least-s ignificant-bit (LS B) firs t. S erial data is clocked onto an internal s ignal (T XD) by the ris ing edge of the transmit clock. T his signal pass es to the Manches ter E ncoder which encodes it and drives the s elected s erial interface. When the encoder is being bypass ed, the serial data drives the XT XD pin directly. 7.6.4 CRC Generator T ransmit Protocol F S M controls trans miss ion of frames, defers to active carriers and collisions , monitors collis ion conditions , and initiates both backoff and re-transmis sion when needed. 7.6.5.1 Interframe Gap and Deference Deference is initiated when both XCR S and XCOL have terminated at the end of a frame. T he trans mitter deference logic initiates a 2-part timer at the end of network activity. While this timer is running, no frame trans miss ion will be initiated. T he firs t part of the timer (interF rame S pacingPart1) is us ed to obs erve the network for transmis sion activity by other s tations . I f this s tation is trans mitting, carrier is s ens ed, or collis ion is detected during this part of the timer, the timer will be reset to zero and held there until the termination of line activity. When the firs t part of the timer elapses , line activity is no longer obs erved and the timer runs to completion. If any frame is queued up for trans mis s ion at the moment of timer expiration, trans mis s ion will be initiated regardless of line activity. T he combination of interF rame S pacingPart1 and i nter F r ame S paci ngP ar t2 makes up the Inter-F rame Gap (IF G) as defined by the 802.3 s pecification. T he interF rame S pacingPart1 is 6.0 s ec and interFrame S pacingPart2 is 3.6 sec. 7.6.5.2 Collision Handling Logic When collis ion is detected by the trans mitter s ection during the firs t s lot time of an active trans miss ion, the transmis sion does not terminate immediately. Ins tead, the preamble is allowed to finish and the jam s equence is transmitted. T he jam s equence consists of 32 bits of logic '1's . If collision is detected after the s lot time is pas s ed, the 83C795 will abort the trans mis s ion with jam and without retry and 'Out of Window Collis ion' bit is s et in the trans miss ion s tatus regis ter. T he trans mitter calculates the CR C s erially and appends it to each frame. CR C is clocked out mos t-significant-bit (MS B) firs t. T he trans mitter can be configured to exclude attachment of the computed CR C by s etting the CR CN option bit in the T r ans mi t Confi gur ati on R egi s ter (T CON.CR CN). T his is us eful for some bridging applications in which the original checks um mus t remain attached to the packet until the final destination. 76 LAN CONTROLLER OVERVIEW 83C795 7.6.6 7.6.6.1 Timers Slot Timer 7.6.6.3 Collision Counter During trans mit, the s lot timer s tarts counting once the receiver recognizes that a carrier is pres ent at the start of a returning preamble. When backing off, the s lot timer s tarts with the end of T XE for the collided frame and does not get reset by any other incoming frames . S l ot ti me i s pr ogr ammabl e thr ough the E nhancement R egis ter. T he choices are 256-, 512-, and 1024-bit times . T he default value is 512-bit times . 7.6.6.2 Backoff Timer After a trans mis s ion is terminated becaus e of a collis ion, a retrans miss ion is attempted. T iming of it is determinedby the 'truncated binary exponential backoff' algorithm. T his algorithm is : draw random integer r: 0 <= r < 2**k where k equals the number of retries already on this trans miss ion. K s tarts at 0. Wait 'r' number of s lot times and then s tart normal trans mit deferral. T he backoff timer is a 12-bit counter that is initialized to a random number when an attempted trans mis s ion res ults in a collision. T he counter decrements once per slot time until it reaches zero. T he T ransmit Protocol S tate machine utilizes this timer to insert a variable amount of delay ahead of its attempt to retrans mit the frame. T here is a s electable enhancement to backoff timer operation which caus es it to s us pend counting while there is network activity and res ume during idle times. In this mode of operation, the backoff timer continues to operate while a carrier s ense remains from the initial collis ion but does not operate during any other carrier indication. T his is referred to as the 'S top Backoff' algorithm. It may put s tations that us e it at a dis advantage when operating on the s ame network with s tations not utilizing it and caution in its use is advised. T his algorithm can be enabled by s etting the S BACK bit in the E NH R egis ter. All retransmis sion attempts are counted by the collis ion counter. After the maximum number of attempts is reached (16), the trans mis s ion of the frame is aborted, an interrupt is generated and event is reported as an error in the trans mit status regis ter. 7.6.6.4 Heartbeat Detection After each transmis sion, the trans mit logic opens a window 3.6 s ec long during which it looks for a puls e on the XCOL s ignal. T his puls e is normally generated by the MAU and is received through the AUI interface. If the pulse is received, the CDH s tatus bit of the T S TAT R egis ter is cleared. If no puls e is received during the window, the CDH bit is s et. 7.6.7 Transmitter Operation 7.6.7.1 Transmission Initialization Packets to be transmitted are built in buffer memory by the host. T hes e packets must include the DA, S A, and data fields. CR C is not read from buffer memory unles s CR C generation is dis abled. T he trans mitter reques ts the frame from the DMA when the T XP bit of the CMD R egis ter is s et by the host. T he T S T ART and T CNT R egis ters mus t be properly programmed prior to s etting T XP. Once set by the hos t, T XP can be cleared only by the DMA after the trans mitter has s ignalled completion of an attempted trans mis s ion. 7.6.7.2 Transmission Process T he DMA s tarts to fill the transmit F IF O with burs ts of data then notifies the trans mitter that it is ready for transmis sion. T he trans mitter defers until the media is clear and an interframe gap has pas s ed then generates preamble and S FD fields . It then pulls bytes out of the trans mit FIFO, s erializes them, and s hifts bits to the output pins while computing the CR C on the packet. T he DMA also monitors the amount of room remaining in the F IF O and initiates a burs t of memory trans fers when there is enough room for the entire burs t to fit. 77 83C795 LAN CONTROLLER OVERVIEW Once the DMA has filled the T ransmit F IF O with the las t byte of the packet, it sets a flag. When the F IF O becomes empty, it signifies the end of the frame. CR C computation s tops and the CR C is appended s erially to the frame, mos t s ignificant bit first. 7.6.7.3 Transmit Underrun If the F IF O becomes empty before the internal flag is s et, it is cons idered a transmit underflow and is posted as a trans mit error in the T rans mit S tatus (T S T AT ) R egis ter. In this cas e, trans miss ion of the packet is aborted and an interrupt can be generated. 7.6.7.4 Early Transmit Underrun Protection T his feature is us ed to facilitate initiation of trans miss ion prior to completion of as s embly of the outgoing frame in the transmit buffer. E arly trans mit underrun protection is controlled by two bits in the Command R egis ter - CMD.DIS E T CH and CMD.E NE T CH. S etting DIS E T CH to '1' dis ables early trans mit underrun checking and s etting E NE T CH to '1' enables checking. Writing both bits to zero leaves trans mit checking in its previous s tate. S etting both bits to '1' is illegal. T his operation works the s ame as the Command R egis ter s tart and s top bits for bringing the chip on and offline. While early transmit underrun checking is enabled, the memory address is latched each time the hos t does a write to the buffer memory (the actual memory addres s is us ed, not the host addres s). When the DMA reads packet data from the buffer memory, the memory address is compared to the mos t recently-latched memory write addres s (written from the hos t with E T CHON only). T he DMA dis tinguis hes between access es to descriptor table entries and actual packet data. If early trans mit checking is on, and the DMA's memory read addres s is greater than the absolute value of the latched memory write addres s , a "buffer underrun" condition is s et. T his condition aborts the trans mitter which in turn aborts the DMA. T he condition is cleared when the DMA detects the abort and clears the trans mit FIFO. T he transmit abort is reported as though it were a F IF O underrun and both the T S T AT.UNDE R and INT S T AT.R XE flag bits are s et. 7.6.7.5 Collisions When a collision is reported on the CD pin, the trans mitter sends a 32-bit sequence compos ed of all '1' bits as a jam signal, then terminates its tr ans mis s ion. If collis ion occur s dur ing the preamble of a frame, the remainder of the preamble is s ent before s ending the jam signal. If the collision occurred after the end of one s lot time, transmis sion is aborted without retry after s ending a jam pattern. T his is cons idered an out-of-window collision and pos ts a s tatus bit in the T S T AT regis ter (T S T AT.OWC) and is a contributor to the T XE flag in the INT S T AT R egis ter. F or collisions that occur within the first slot time of a frame, a counter of retries is incremented and checked agains t the retry limit (16). If the number of retries is less than the limit, a back-off delay (in units of s lot-time) is chos en at random. T he tr ans mi tter then r eques ts the fr ame's retransmis sion from memory and delay is initiated. T he DMA controller clears out the transmit F IF O, loads its pointer to the start of frame in memory, and waits for the abort s ignal to s ubside. T he F IF O is loaded in the same manner as it was initially. If the maximum number of collis ions (16) is exceeded, trans miss ion is aborted without further retries and no back-off delay is executed. 78 LAN CONTROLLER OVERVIEW 83C795 7.6.7.6 Extensions Beyond 802.3 10Base5 Protocol T he 802.3 10Bas e5 protocol utilizes frame lengths between 64 and 1518 bytes inclus ively. T he trans mitter s ection is capable of sending frames greater than 17 and les s than 32,768 bytes in length. T ransmis sion of longer or shorter frames than permitted within the 10Base5 definition may be useful in other variations of 802.3 protocols. When considering the trans mis s ion of giant frames on a non-802.3 network, be aware that very long frames can activate jabber detectors in exis ting 10Bas eX MAUs and repeaters . T he use of s uch fr ames in non-s tandard networks requires cons iderable planning and s ome caution. To s upport non-802.3 protocols, the 83C795's s lot time is program-selectable. Choose from 256-bit, 512-bit, or 1024-bit times. T he S top Backoff algorithm is s electable for backoff modification following collis ions . When operating in ALT E GO Mode, detection of any pair of consecutive '0' bits within the preamble caus es the reception of that fr ame to be abandoned. No error is reported. T he R CON.R CA bit enables the receiver to abandon reception of any frame which caus es a collis ion. No error is reported. 7.6.7.7 Extended Length When the XL E NGT H bit (GCR .7) is s et, the twisted-pair port can be connected to cables longer than the 100-meter limit specified by the 802.3 s pecification 79 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 8.0 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES TRANSMIT PACKETS Single Packet Transmission 8.1 8.1.1 A packet for transmis sion is placed by the hos t into buffer memory. T his packet must include the DA, S A, and data fields. T he preamble, S F D, and CR C (normally) are not included in the buffer. If CR C generation is s uppress ed, the CR C field for the packet is also s upplied by the hos t. T he packet is placed in a contiguous block of memory in the buffer, s tarting on a 256-byte boundary. Valid 802.3 packets have at least 48 bytes of data. If les s data is to be trans mitted on an 802.3 network, it is the res pons ibility of the host to build a packet with pad data included. T he 83C795 will transmit frames of any programmed length (greater than 17 bytes), even thos e which are too s hort to be valid frames in an 802.3 network. DMA will trans fer the number of bytes programmed into the T CNT H and T CNT L R egis ter pair s tarting fr om addres s (T S TAR T * 100H). 8.1.2 Multiple Packet Transmissions form pres ently expected. T he driver then adds an entry for each frame into a table of trans mit descriptors . T his entry contains the s tarting location and length, and trans mit configuration for each frame in the trans mit queue. Places are provided in the table for return of the T rans mit S tatus (T S T AT ) R egis ter and collision count ass ociated with each trans miss ion. A simple s emaphore protocol will be us ed to control ownership of trans mit buffers . T he LAN controller keeps a pointer in the T T ABH and T T ABL R egis ters to the trans mit descriptor table. T his pointer is initialized by the driver when the table is firs t built and s hould not need re-initialization thereafter. When transmit command has been s et and device is online, trans mit begins from the entry pointed to by the T T ABH and T T ABL R egis ters . T he LAN controller firs t checks the T S T AT field. If it encounters a field equal to F F, it will attempt to transmit the frame pointed to by the entry. T he s tatus field will be changed to zero after the remainder of the entry has been read. When it encounters a T S T AT field not equal to F F, no frame will be s ent, the trans mit complete interrupt will be s ent and the field will not be altered. If the frame is marked for trans mis s ion, the DMA controller loads its T S T AR T H, T S T AR T L, T CNT H, T CNT L, and T CON R egis ters from the des criptor. T S T AT gets marked as having been opened by the LAN controller and trans mis s ion proceeds as with s ingle tr ans mis s ions except that when the trans miss ion has completed, the trans mit status and collision count are moved by DMA into the table. T he table pointer is updatedandtransmis sion of next entry begins. If a transmit abort occurs (too many collis ions ) the trans mitter will stop proces s ing the chain and pos t the current trans mit and interrupt s tatus . If the CMD.S T P bit is s et, the trans mis s ion of any ongoing frame proceeds until completion or abort but no s ucces s ive fr ames in the chain are process ed. T he T T AB indices will point to the firs t unproces s ed frame in the table s o that none are los t. An alternative mode of controlling the transmit interrupt can be enabled by the E OT INT bit in the E nhancement (E NH) R egis ter. When enabled, the trans mit interrupt will be generated only upon To s upport multiple trans mis s ions per command, a trans mit queue can be enabled by s etting the ALT E GO bit in the E nhancement R egis ter (E NH.5). In this mode, a table of frame descriptors defines the s tarting location and length of all enqueued trans miss ions . T his des criptor table is process ed in a circular manner by the LAN controller. T he table is treated as a ring of entries whose s tarting and ending points are defined by a pair of regis ter s (T B E GI N and T E ND) in the L AN controller. T hes e regis ters are initialized with the upper 8-bits of address for the firs t location of the table and the first location after the end of the table. T E ND is not within the table. When table proces sing reaches the location definedby T E ND, it is s witched back to T BE GIN. T he table mus t be aligned with 256 byte boundary in the buffer memory. E ach entry is 8 bytes long. T he format of this buffering is defined in F igure 8-1. To s endmultiple trans mis s ions, the driver builds the frames in buffer memory in the same contiguous 80 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795 FIGURE 8-1. MULTIPLE FRAME TRANSMIT BUFFER FORMAT 81 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES completion of the trans mit chain. Normal mas king applies on top of this delay mechanism. Without enabling this new mode of controlling trans mit interrupts, an interrupt will be generated on a frame by frame bas is but the interrupt s tatus may not be current by the time it can be readby the driver s oftware. 8.1.2.1 Ownership of Buffers T he T S T AT field of the table entry is us ed to control owners hip of the frame buffers . Hands hake over control of trans mit frame buffers is governed by the following conventions : TSTAT Field Value TSTAT field = 00 Meaning defines the end of the enqueued frames for the DMA. S et the T XP bit of the COMMAND register to ens ure that the new trans mis s ion goes out. T he T XP bit can be written regardless of completion status and will ensure that the latest frame does get trans mitted. If the LAN controller reaches the end of the transmit queue before the new frame has been added, a trans mit complete interrupt is generated for the old portion of the queue and another trans mit complete interrupt will be generated when the added portion completes. T he driver s hould not attempt to alter any buffered frame whos e T S T AT is either 00 or F F while CMD.T XP is turned on. Wait until all trans mis s ions are complete or set the CMD.S T P bit and wait for the S T OP status to be confirmed in the Interrupt S tatus regis ter. E xamine T S T AT table entries to determine which frames have been transmitted. T hos e whose entries are F F have not been opened by trans mitter. R efer to Tables 8-2 and 8-3 for a s ummary of the trans mit descriptor table format. 8-BIT MEMORY COLCNT TSTAT TSTARTL TSTARTH TCNTL TCNTH TCON not used TABLE 8-2. FORMAT OF TRANSMIT DESCRIPTOR TABLE 16-BIT MEMORY D15-D08 TSTAT TSTARTH TCNTH not used D07-D00 COLCNT TSTARTL TCNTL TCON 83C795 has begun transmission. TSTAT field > 00 and < Frame completed. FFh TSTAT field = FF Assembled frame, not yet transmitted. TABLE 8-1. TSTAT FIELD VALUES T he driver s oftware fills the T S T AT table entry with F F h when it releas es the frame to the LAN controller for trans mis s ion. When trans mit command has been s et and device is online, the DMA looks at T S TAT field. If it encounters a field = F F, it will attempt to transmit the frame pointed to by the entry. T he s tatus field will be changed to zero after descriptor entry is read and trans mitter commits to s ending. If DMA encounters a T S T AT field greater than or les s than FF h, no frame will be transmitted, the trans mit complete interrupt will be sent. T he field is not altered. When a transmis sion completes, the contents of T S TAT regis ter will be moved into that location. 8.1.2.2 Modifying the Transmit Queue To add a frame to the transmit queue, build the frame in buffer memory then find the table entry following the las t enqueued frame. E nter the descriptor for the new frame with a T S T AT that is neither 00 nor F F in value. When des criptor is complete, write T S T AT with FF. T he des criptor entry following the las t enqueued frame entry must have its T S TAT value marked with a non-F F value. T hat 82 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795 REG COLCNT DESCRIPTION Written with the number o f collisions experiences by the LAN controller while attempting to transmit this frame. This entry in the table is used to control ownership of the frame buffer: TSTAT = 00 means the 83C795 has begun transmission TSTAT>00 but RECEIVE PACKET BUFFERING T wo alternative modes of buffering received packets are s upported: ring of buffers and linked-list. S election between thes e two modes is made by a bit in the E NH R egister, E NH.ALT E GO. 8.2.1 Ring of Buffers All received packets are stored in one circularly connected, contiguous s et of 256-byte buffers . T he number and location of buffers in the ring is determined by the values written into the R S TART and R S T OP R egis ters by the hos t when the 83C795 is initialized. R S T AR T points to the firs t buffer in the ring and R S T OP points to the buffer after the las t one in the ring. E ach packet received will be s tored into one or more of these buffers , with a4-byte header ins erted at the s tart of the firs t buffer. F igure 8-2 details the format of a received packet in memory. TSTAT TSTARTH,L TCNTH, L TCON not used TABLE 8-3. MEANING OF DESCRIPTOR TABLE 83 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES FIGURE 8-2. RECEIVER BUFFER FORMAT 84 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795 F rames that extend to the buffer des ignated by R S T OP are continued in the buffer des ignated by R S T AR T and succes s ive locations. R S T OP may be either greater than R S T AR T +1 or les s than R S T AR T. Making R S T OP equal to R S T ART or R S T AR T + 1 leads to unpredictable res ults . T he relations hip of thes e registers to ring placement in memory is illus trated in F igure 8-3. Up to 254 buffers can be allocated to the ring. T he receiver DMA will us e as many as required to s tore a packet. T his allows the chip to be configured to receive frames nearly as long as 64K bytes. T his can be us eful in cus tomiz ed CS MA networks ; however, allocating s o many buffers to the reception proces s leaves very little capability for buffering trans mit frames although it is within the capability of the 83C795. T he receive DMA utilizes two additional regis ters to manage the buffer ring. T hes e are the Current Page R egis ter (CUR R ) and the Boundary Page R egis ter (BOUND). T he CUR R R egis ter points to the firs t buffer that is not part of a completely received packet. When R DMAis s toring aframe, this regis ter points to the s tart of the frame being s tored. When R DMA is not s toring a frame, it points to the firs t buffer that will be used for the next frame to be received. T he BOUND R egis ter protects received frames from being overwritten by later frames. It points to the first buffer in the ring that is not to be overwritten. FIGURE 8-3. RING BUFFER STRUCTURE 85 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES When the receive DMA process attempts to open the buffer that BOUND points to for s torage of a packet, it aborts the reception and s ets the I NT S T AT .OVW flag (in the Interrupt S tatus R egis ter) and the R S T AT.MPA bit (in the R eceiver S tatus R egis ter). T he protected buffer is not written to. Normally, BOUND is s et up to point to the oldes t received packet in the ring. T his pointer can be managed by the host. To dis card an unwanted frame, the host may s imply rewrite BOUND to point to the next packet. A good practice is to write zeros into the firs t byte of the dis carded packet to prevent future interpretation as a received packet. When BOUND and CUR R have the same value, the ring may be either full or empty. T he 83C795 can dis tinguis h between full and empty rings . CUR R is updated by the DMA controller at the end of a frame reception. T he ring is cons idered full if thes e two regis ters are equal and the DMA controller updated CUR R more recently than the host updated BOUND. Convers ely, when data is being removed from the ring, the hos t updates BOUND after removal. When it has been advanced past the end of the last received frame, it s hould have the same value as CUR R . T he chip treats the ring as empty when these two regis ter values are equal and BOUND has been updated after CUR R . When initializing the buffer ring, BOUND andCUR R may be given the s ame or different values. T hese regis ters may be initialized to point to any buffer within the ring. T hey may point to R S T AR T but may not point to R S T OP. If CUR R points outside the ring, the R DMA will s tore frames outside the ring in an unpredictable manner. If BOUND points outs ide the ring, the received frames will not be protected from overwrites by later frames. F igure 8-4 illus trates the buffer ring in two common s tates . T he top ring, INIT R B UF, illus trates the relations hip between thes e pointers in a typical ring initialization. T he bottom ring, R BUF, s hows a ring that has received a few frames - the normal condition for the ring. FIGURE 8-4. RECEIVER BUFFER RING 1 86 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795 FIGURE 8-5. RECEIVER BUFFER RING 2 F igure 8-5 s hows the s ame ring after proper removal of the oldes t received packet. T he top ring, F ULLR ING, s hows a ring that is completely full. T he bottom ring, OVE R F LOW, s hows a ring on the verge of overflow. 8.2.1.1 Automatic Ring Wrapping Automatic ring wrapping enables the hos t to read a contiguous block of data from the buffer R AM without having to check whether the block is s o long that the acces s wraps around the end of the buffer ring. T his is accomplished by checking whether the next value to be loaded into the memory cache's buffer counter is equal to the regis ter R S T OP. If this is true, then the value of the R S T AR T regis ter is loaded into the counter ins tead. T he memory cache's Hos t Counter is left unchanged s o the hos t can continue acces sing memory pas t the end of the ring, but ins tead receives the correct data from the s tart of the ring. T he comparis on is only made when the counter is incrementing so it is not pos sible to s tart the block of data pas t the ring's end. Als o, s ince the hos t is sending address es that are greater than the end of the ring, it is required that the 83C795's memory s pace extend beyond the end of the ring. T his can be accomplis hed by arranging the memory s pace s uch that the trans mit buffers come after the receive buffer ring. T his feature is enabled by s etting the WR APE N bit (UBR CV.0). F or more on this , refer to page 40. 8.2.1.2 Ring-Empty Bit T his is a read-only bit located at UBR CV.2 which indicates to the hos t that there are no completely received frames in the buffer ring yet. T he hos t checks this bit after it finis hes receiving a frame and quickly determines whether there are more frames to copy. T his bit is s et when BOUND equals CUR R . BOUND is updated after CUR R . S ince this bit is only cleared for completely received frames, another method mus t be us ed to determine if there is a partial frame in the buffer that exceeds 87 83C795 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES the early receive threshold (early receive mode only). T his is done by checking the interrupt status regis ter after checking the ring-empty bit. 8.2.2 Linked-List Receiver Buffering s ize, and us age of all receiver buffers . T his table controls both the received frames and the available buffer pool. T he des criptor table is treated as a ring of entries whose s tarting and ending points are defined by a pair of regis ters (R BE GIN and R E ND) in the LAN controller. T hes e regis ters are initialized with the upper 8-bits of address for the firs t location of the table and the first location after the end of the table. R E ND is not within the table. When table process ing reaches the location defined by R E ND, it is switched back to R BE GIN. T he table mus t be aligned with 256-byte boundary in the buffer memory. E ach entry is 8-bytes long. T he format of this buffering arrangement is depictedin Figure 8-6. Linked-List R eceiver Buffering is enabled by a bit in the E nhancement regis ter, E NH.ALT E GO, and is an alternative to receive ring form of buffering. In this mode, the receiver directs its input to a group of individually-s ized buffers that are not neces s arily contiguous . All buffers need not be the s ame s ize. Multiple buffers can be chained together as needed to receive an incoming frame. T hes e buffers are linked together via a table of buffer des criptors which define the s tarting location, FIGURE 8-6. LINKED-LIST BUFFER FORMAT 88 BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES 83C795 T he LAN controller keeps a pointer (R egis ters R T AB H and R T ABL) to the R eceive Descriptor table. T his pointer is initialized by the driver when the table is firs t built and s hould not need re-initialization thereafter. When the LAN controller's DMA becomes active to receive a frame, it will use RT AB as a pointer to the firs t free receive buffer. R S TAT field of descriptor is checked to s ee if the buffer is free (R S T AT =00). If free, the s ize and s tarting location of the buffer are loaded from the des criptor and rounded down to even values. S torage of the frame into the buffer begins . T he value of RT AB is s aved at the s tart of reception for each frame in cas e the frame gets aborted and RT AB has already been updated to the next table entry. While a frame is being buffered, the LAN controller will follow the entries in the des criptor table to obtain additional buffers as needed to receive the entire frame. Upon completion, the des criptor for the firs t buffer of that frame is written with the receiver status regis ter and the total byte count for that frame. T he byte count includes storage of the received F CS . S hould a partially received frame be rejected by the LAN controller, it will reclaim the buffers by res etting the RT AB pointer to its value previous to s tart of reception of this frame. To addfree buffers to the endof the des criptor table, fill in the first new table entry with R S T AT =non-zero, build all other table entries with R S T AT =0, then change the firs t R S T AT to 00 to indicate availability. 89 83C795 ELECTRICAL SPECIFICATIONS 9.0 ELECTRICAL SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V TTL Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 - 5.5V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 - 5.5V Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 - 16V Differential Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C (-85F) to 150C (302F) Abs olute maximum ratings indicate limits beyond which permanent damage may occur. Continuous operating at thes e limits is not recommended; operation s hould be limited to conditions s pecified under "DC Operating Characteris tics ." 9.2 RECOMMENDED OPERATING CONDITIONS Supply Voltage (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 5% Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C (32F) to 70C (158F) 9.3 DC OPERATING CHARACTERISTICS T a = 0 C (32 F ) to 70 C (158 F ) Vdd = +5V 5% Note All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. 9.3.1 Input Pins MIN MAX 110 -- UNIT mA V CONDITIONS SYMBOL PARAMETER S upply Current I dd Vih Input High Voltage (MA09-MA00) 2.0 Internal pull-down resistor value between 35K and 150K. when Vcc=4.5V when Vcc=5.5V for S chmitt-triggered inputs, T T L-compatible levels CMOS level input T T L levels , high impedance Input High Voltage (MA07-MA00, ME MR , ME MW, S BHE ) 1.65 1.94 -- -- V V Input High Voltage (X1) Input High Voltage (All other inputs ) 3.5 2.0 -- -- V V 90 ELECTRICAL SPECIFICATIONS 83C795 SYMBOL PARAMETER Vil Input Low Voltage (MA09-MA00) MIN -- MAX 0.8 UNIT V CONDITIONS Internal pull-down resistor value between 35K and 150K. when Vdd=4.5V when Vdd=5.5V Internal pull-down resistor value between 35K and 150K. CMOS level input when Vdd=4.5V when Vdd=5.5V when Vdd=4.5V when Vdd=5.5V when Vdd=4.5V when Vdd=5.5V when Vdd=4.5V when Vdd=5.5V Input Low Voltage (MA07-MA00, ME MR, ME MW, S BHE ) -- -- 1.04 1.20 V Input Low Voltage (X1) Input Low Voltage (All other inputs ) Vhys Vt+ VtVds Input Voltage Hys teres is (S chmitt Inputs ) Input Voltage T T L + (S chmitt Inputs ) Input Voltage T T L(S chmitt Inputs ) Differential S quelch T hreshold (R X, CD) Differential S quelch T hreshold (T PR ) Input Low Current (R X, CD, T PR ) Input Low Current (MA09-MA00, MD07-MD00, ME MR , ME MW, S BHE ) Input Low Current (X1) Input Low Current (All other inputs ) Input High Current (R X, CD, T PR ) Input High Current (X1) Input High Current (All other inputs ) Input Current (CAP) -- -- -- 0.40 0.39 1.45 1.65 1.04 1.20 -175 300 -- -25 1.5 1.04 1.20 0.51 0.59 1.65 1.94 1.18 1.35 -300 500 -500 -200 V V V V V V V V V mV mV uA uA I il -- -- -- -- -- -1.0 -50 -10 500 50 10 -1.0 uA uA uA uA uA mA when Vin = 2.5V I ih I in TABLE 9-1. INPUT PIN VALUES 91 83C795 ELECTRICAL SPECIFICATIONS 9.3.2 Output Pins MIN MAX 0.7 0.6 0.75 0.4 0.4 UNIT V V V V V CONDITIONS Iol = 8mA I ol = 30mA I ol = 14mA I ol = 24mA I ol = 24mA SYMBOL PARAMETER Vol Output Low Voltage (X2) Output Low Voltage (T PX1 ) Output Low Voltage (T PX2) Output Low Voltage (Z WS ) Output Low Voltage (GPOUT, IOR DY, IO16CS , M16CS , S D00-S D16) Output Low Voltage (All other outputs ) Output High Voltage Voh (X2) Output High Voltage (T PX1) Output High Voltage (T PX2) Output High Voltage (Z WS ) Output High Voltage (GPOUT, IOR DY, IO16CS , M16CS , S D00-S D16) Output High Voltage (All other outputs ) Vod Differential Output Voltage (T X) 0.4 3.5 Vdd-0.6 Vdd-0.75 2.4 2.4 V V V V V V I ol = 4mA Ioh = -100mA I oh = 30mA I oh = 14mA I oh = 24mA I oh = 24mA 2.4 -500 500 -1200 1200 V mV mV I oh = 4mA 78 termination and 150 from each output to Vdd. 10.0 K external res is tor to Vdd. 24.9 K external res is tor to Vdd. Vout Output Voltage (BS R ) Output Voltage (OS R ) 2.25 2.75 V 2.25 2.75 V TABLE 9-2. OUTPUT PIN VALUES 92 AC OPERATING CHARACTERISTICS AND TIMING 83C795 10.0 AC OPERATING CHARACTERISTICS AND TIMING T his s ections provides timing diagrams and parameters for 83C795 s ignals . Table 10-1 indicates the timing diagrams included in this s ection. Table 10-2 indicates the timing parameters applying to each timing diagram. E xcept where otherwis e noted, timing units are in nanos econds. FIGURE 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 TITLE S ystem Clock T iming R egister Acces s T iming - R ead R egister Acces s T iming - Write 16-bit R egis ter Acces s (I/O Pipe Only) Host Memory Access (16-bit, Z WS ) Host Memory Access (8-bit, No Z WS ) Host Memory Access (8-bit, Z WS ) Host Memory Access (8-bit, No Z WS ) R om Acces s (8-bit Only, R ead Only) DMA or Memory Cache Writes DMA or Memory Cache R eads E E PR OM Interface T rans mit T iming - S tart Of T rans mis s ion T ransmit T iming - End Of T ransmission (last bit = 1) T ransmit T iming - End Of T ransmission (last bit = 0) R eceive T iming - S tart Of Packet R eceive T iming - E nd Of Packet Collis ion T iming - AUI Collis ion T iming - T P Loopback T iming S QE Test T iming Link Tes t Puls e R OM Dump (Tes t Mode) TABLE 10-1. LIST OF TIMING DIAGRAMS 93 83C795 AC OPERATING CHARACTERISTICS AND TIMING PARAMETER T1 T2 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 20 T 21 T 22 T 23 T 27 T 28 T 29 T 30 T 31 T 32 T 33 T 35 T 36 T 41 T 42 T 43 T 46 T 48 T 49 T 50 T 51 T 52 DESCRIPTION R egis ter R ead: data valid delay R egis ter R ead: data hold time Addres s setup for regis ter I/O Addres s hold for regis ter I/O IOR DY inactive delay from I/O s trobe IOR DY active delay from X1 IOR DY tris tate delay from I/O s trobe R egis ter write: data s et up time R egis ter write: data hold time IOW active time IOR active time MCS 16 active from LA addres s (FINE 16=0) M16CS inactive from LA addres s IO16CS active from S A address IO16CS inactive from S A address IOR DY active delay from HOS T CLK Z WS tris tate delay from S ME Mx s trobe Z WS active from ME Mx strobe (16 bit) Z WS tris tate from ME Mx s trobe S ME MR active to inactive S ME MR active to R OMCS active R OMCS active to S D valid R OM read: data hold time S A addres s setup for ME Mx s trobe S A adres s hold for ME Mx s trobe IOR DY inactive delay from ME M s trobe IOR DY active delay from X1 IOR DY tris tate delay from ME M s trobe Z WS active delay from HOS T CLK E E CS s et up time E E CS hold time R LE D s et up time R LE D hold time E E DO delay MIN 3 - - - - - - 15 20 300 300 - - - - - - - - 425 - - 15 18 - - - - - 100 100 100 100 - - - - - - - - - - - - - - - - - - 9 - - - - - - - - - - - - - - - - TYP MAX 5 15 18 0 20 28 14 - - - - 15 13 17 15 25 11 13 11 - 155 270 - - 0 23 27 17 17 - - - - 200 UNITS Cycles nsec TABLE 10-2. TIMING PARAMETERS 94 AC OPERATING CHARACTERISTICS AND TIMING 83C795 PARAMETER T 53 T 54 T 57 T 58 T 59 T 60 T 61 T 62 T 64 T 65 T 66 T 67 T 68 T 69 T 70 T 71 T 72 T 73 T 74 T 75 T 76 T 77 T 78 T 79 T 80 T 81 T 82 T 83 T 84 T 85 T 86 T 87 DESCRIPTION MA addres s active delay from X1 MA addres s inactive delay from X1 R AMWR active delay from X1 R AMWR inactive delay from X1 MA addres s s et up to R AMWR , R AMOE MA addres s hold from R AMWR Data valid delay time from X1 Data hold time from R AMWR R AMOE active delay from X1 R AMOE inactive delay from X1 Data s etup time to X1 Data hold time to X1 XT XE s etup time to XT XC XT XE hold time from XT XC XT XD hold time from XT XC T X outputs delay to idle T X outputs stay high before idle XT XD s etup time to XT XC T X outputs delay from XT XC - AUI T X outputs delay from XT XC - T P XCOL active delay - AUI XCOL active delay - T P XCOL inactive delay - AUI XCOL inactive delay - T P XCR S active delay - AUI XCR S active delay - T P XCR S inactive delay - AUI XCR S inactive delay - T P Differential input reject puls e width - AUI Differential input reject puls e width - T P Acquisition time from PLL - AUI Acquisition time from PLL - T P XR XD s table from XR XC S QE tes t start delay - T P S QE tes t duration - T P Loopback s etup time Loopback hold time MIN - - - - 10 15 - 15 - - 12 0 25 0 0 - 240 20 - - - - - - - - - - 8 8 - - 40 - - - - TYP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20 - - - 900 1000 - - MAX 26 10 11 9 - - 24 - 12 9 - - - - - 310 - - 100 100 60 900 350 160 300 60 250 160 35 30 700 950 - - - - - UNITS nsec TABLE 10-2. TIMING PARAMETERS (cont.) 95 83C795 AC OPERATING CHARACTERISTICS AND TIMING PARAMETER T 88 T 89 T 90 T 91 T 92 T 93 T 94 DESCRIPTION X1 clock period X1 clock width high X1 clock ris e time X1 clock fall time X1 clock width low Link tes t puls e width I/O write recovery time MIN 45 22.5 - - 22.5 - 2 TYP 50 25 - - 25 100 - MAX - - 3 3 - - - UNITS nsec cycles TABLE 10-2. TIMING PARAMETERS (cont.) NOTES 1. All numbers are in nanoseconds except where otherwise designated. 2. All outputs are measured under 50pF load. 3. The external Manchester Encoder/Decoder port is multiplexed out on other pins in certain test modes only. Use the table below to determine which Manchester signals correspond to which pin names. MANCHESTER SIGNALS XTXD XLOOP XCRS XRXC XRXD XCOL XTXC XTXE 83C795 I/O PINS IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ROM CS TABLE 10-3. TEST PIN I/O MATCHING Refer to Chapter 4 for more details. 96 AC OPERATING CHARACTERISTICS AND TIMING 83C795 T88 T90 T91 90% 10% T89 T92 X1 FIGURE 10-1. SYSTEM CLOCK TIMING X1 BALE T6 SA15 - SA00 ADDRESS VALID T7 T14 IOR T8 IORDY T9 T10 T1 SD7 - SD0 DATA VALID T2 FIGURE 10-2. REGISTER ACCESS TIMING - READ 97 83C795 AC OPERATING CHARACTERISTICS AND TIMING X1 BALE T6 SA15 - SA00 ADDRESS VALID T7 T13 IOW T8 IORDY T9 T10 T11 SD0 - SD7 T12 DATA FIGURE 10-3. REGISTER ACCESS TIMING - WRITE X1 SBHE SA15 - SA00 ADDRESS VALID T6 IOR, IOW T7 T21 IO16CS T22 T41 IORDY T42 T43 FIGURE 10-4. 16-BIT REGISTER ACCESS (I/O PIPE ONLY) 98 AC OPERATING CHARACTERISTICS AND TIMING 83C795 HOSTCLK SBHE BALE LA23 - LA17 VALID SA15 - SA00 ADDRESS VALID T35 MEMR, MEMW T36 T15 M16CS T20 T28 ZWS T29 T43 IORDY FIGURE 10-5. HOST MEMORY ACCESS (16-BIT, ZWS) 99 83C795 AC OPERATING CHARACTERISTICS AND TIMING X1 SBHE BALE LA23 - LA17 VALID SA15 - SA00 ADDRESS VALID T35 MEMR, MEMW T36 T20 T15 M16CS T41 IORDY T42 T43 FIGURE 10-6. HOST MEMORY ACCESS (16-BIT, NO ZWS) 100 AC OPERATING CHARACTERISTICS AND TIMING 83C795 HOSTCLK SBHE BALE LA23 - LA17 VALID SA15 - SA00 ADDRESS VALID T35 SMEMR, SMEMW T36 T46 ZWS T27 T41 IORDY T23 T43 FIGURE 10-7. HOST MEMORY ACCESS (8-BIT, ZWS) 101 83C795 AC OPERATING CHARACTERISTICS AND TIMING X1 SBHE BALE LA23 - LA17 VALID SA15 - SA00 ADDRESS VALID T35 SMEMR, SMEMW T36 T41 IORDY T42 T43 FIGURE 10-8. HOST MEMORY ACCESS (8-BIT, NO ZWS) 102 AC OPERATING CHARACTERISTICS AND TIMING 83C795 HOSTCLK SA15 - SA00 ADDRESS VALID T35 SMEMR T30 T36 T31 ROMCS T32 SD7 - SD0 T33 DATA VALID FIGURE 10-9. ROM ACCESS (8-BIT ONLY, READ ONLY) 103 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-10. DMA OR MEMORY CACHE WRITES 104 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-11. DMA OR MEMORY CACHE READS 105 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-12. EEPROM INTERFACE 106 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-13. TRANSMIT TIMING - START OF TRANSMISSION 107 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-14. TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 1) 108 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-15. TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 0) 109 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-16. RECEIVE TIMING - START OF PACKET 110 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-17. RECEIVE TIMING - END OF PACKET 111 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-18. COLLISION TIMING - AUI FIGURE 10-19. COLLISION - TP 112 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-20. LOOPBACK TIMING FIGURE 10-21. SQE TEST TIMING 113 83C795 AC OPERATING CHARACTERISTICS AND TIMING FIGURE 10-22. LINK TEST PULSE 114 AC OPERATING CHARACTERISTICS AND TIMING 83C795 FIGURE 10-23. ROM DUMP (TEST MODE) 115 83C795 PACKAGE DIMENSIONS 11.0 PACKAGE DIMENSIONS F igure 11-1 illus trates the 160-pin PQF P package. FIGURE 11-1. 160-PIN PQFP PACKAGE 116 PACKAGE DIMENSIONS 83C795 LETTER A A1 A2 D D1 E3 E1 H L MIN 0.05 3.10 30.95 27.90 30.95 27.90 0.10 0.65 NOM MAX 4.07 0.5 3.67 L P W R1 R2 TD TE 0 MIN NOM 1.60 0.65BSC 7 MAX 31.20 28.00 31.20 28.00 0.80 31.45 28.10 31.45 28.10 2.20 0.95 0.20 0.20 0.30 30.45 30.45 0.40 TABLE 11-1. PACKAGE DIMENSIONS Notes: 1. Coplanarity is 0.100 mm. maximum. 2. Tolerance on the position of the leads is 0.120 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimensions TD and TE are important for testing by robotic handler. 5. Dimensions for foot length L when measured at the centerline of the leads are given at the table. Dimension for foot length L when measured at the gauge plane 0.25 mm above the seating plane, is 0.78-1.03 mm. 6. Controlling dimension is millimeter. 7. Details of pin 1 identifier are optional but must be located within the zone indicated. 117 83C795 INDEX ! 10BASE-T status LED driver reading back 29 16-bit host bus indicator 51 16-bit response to host access 51 83C585 compatibility with 83C790 19 83C690 similarities to 83C790 1 83C790 operating conditions 90 A Abort transmission field 39 AC operating characteristics 93 Accessing LAN register 67 Address decoders 46 Address generation path 49 Address modifiers 48 Address recognition logic 71 AEN 6 Alignment error counter register 23 ALTEGO 80 See buffering format selection Arbitration internal bus 50 AUI Collisions 6 AUI differential driver transmitter 74 AUI differential receiver receiver 69 Auto-configuration ports 57 Automatic polarity correct field 29, 75 Automatic ring wrapping 87 Avoiding SA and LA line conflicts 51 B Backoff counter field 24 Backoff timer 77 BALE 6 BIOS page register 17 Block diagram 1 Board ID register 19 Boundary page register 85 Broadcast frames 71 receiving 32 BSR 6 Buffer memory decoding 47 Buffer room remaining count registers 32 Buffer structure and data movement processes 80 - 89 Buffer underrun field 39 Buffer window size field 20 Buffering format selection field 26, 79 Burst starting address 35 C CAP 6 Carrier sense 69 Carrier sense lost field 39 Carrier sense monitoring 39 CD 69 CD+/CD- 6 Chaining multiple buffers 88 Check addresses/CRC without buffering field 31 Chip type indication field 18 Collision count register 24 Collision counter 77 Collision counter field 25 Collision detect heartbeat field 39 Collision detection 78 receiver 69 Collision handling logic 76 Collision translator 74 Command register 23 - 24, 78 Configuration register 55 Configuring Plug and Play as a boot card 64 Configuring Plug and Play with an I/O-mapped pipe 64 Control register 14 Controller registers 12 Conventions 3 Counter overflow enable field 27 Counter overflow field 28 Counting packet collisions 24 CRC checking 71 CRC error counter 25 CRC error field 33 CRC generation inhibition field 37 CRC generator 76 WAKE 59 Current frame buffer descriptor pointer registers 25 Current frame buffer pointer register 25 D Data configuration register 26 Data path description 3 118 83C795 DC operating characteristics 90, 92 Deserialization of the receiver 70 Designating linked-list buffering 26 Designating ring buffering 26, 79 Designating the next DMA buffer 30 Determining the cause of an interrupt 28 DMA controller 65 assembly and disassembly latches 65 loopback testing 65 memory interface 68 memory interface unit (MIU) 65 microcontroller 67 DMA controller next buffer register 30 DMA memory interface 67 DMA microcontroller 67 E Early receive warning 71 Early receive warning count register 71 Early receive warning enable field 27 Early receive warning field 28 Early transmit checking 78 Early transmit checking (ENETCH & DISETCH) fields 24 Early transmit underrun protection 78 EECS 6 EEDO 6 EEROM interface overview 54 recall operations 54 register logic 55 storage of user-defined initial configurations 57 storage of user-defined LAN address 57 storage operations 56 unlocking write operations 56 EEROM address field 15 EEROM controller and its utilization 53 EEROM register 14, 54 Electrical specifications 90 - 92 Emitter-coupled logic 74 Enable interrupts field 17 End-of-transmit interrupt 26 Enhancement register 23, 26, 77 ERFBIT 72 ERW interrupt 71 Extensions beyond 802.3 79 External power supply control 64 F Features 1 FIFO structure 68 FIFO overrun field 33 FIFO underrun field 39 Frame alignment error field 33 Functional description 3 G General control register 21 - 22 General description 1 General purpose output (GPOUT) field 21, 64 Giant frames accommodating on a non-802.3 network 79 GPOUT 64 GPX pin value selection 16 Group address recognized field 33 H Hardware support register 16 Heartbeat detection 77 Heartbeat test 75 High RAM address field 20 Host bit width selection 16 Host interface address decoders 46 basic functions 44 EEROM controller and its utilization 53 I/O address decode 50 I/O-mapped pipe 46 internal bus arbitration 50 interrupt request control logic 52 introduction 44 memory address generation 48 memory bus structure 51 memory cache 44 Plug and Play 57 zero wait state response to the host 50 Host interface internal registers introduction 14 Host registers BIOS page register 17 board ID register 19 control register 14 EEROM register 14 general control register 21 - 22 hardware support register 16 I/O address register 19 LAN address registers 18 POS ID registers 19 RAM address register 20 ROM control register 20 119 83C795 HOSTCLK 6 HRAM 64 I I/O address decode 50 I/O address register 19 I/O-mapped pipe 46 IGSM deferral field 33 INIT pins See MA03-MA00 Initialization 53 Initialize EEROM jumpers 15 INITRBUF 86 Inter-frame gap definition 76 Interframe gap and deference 76 Internal bus arbitration 50 LAN controller 67 Interrupt disabling 52 Interrupt mask register 27 Interrupt on end-of-transmit field 26, 82 Interrupt request control 52 Interrupt request field 21 Interrupt status field 16 Interrupt status register 28 INTMASK 71 IOR 6 IORDY 6, 44, 50, 67 IOW 6, 67 IPL ROM code 51 IRQ lines 6 J Jabber protection 75 Jumper6 22 L LA address bus 7 LAN address registers 18 LAN controller DMA 65 DMA memory interface 67 DMA microcontroller 67 FIFOs 68 how to access registers 67 internal bus arbitration 67 overview 65 - 79 receiver network interface 68 LAN controller registers alignment error counter register 23 buffer room remaining count registers 32 collision count register 24 command register 24 CRC error counter 25 current frame buffer descriptor pointer registers 25 current frame buffer pointer register 25 data configuration register 26 DMA controller next buffer register 30 enhancement register 26 interrupt mask register 27 interrupt status register 28 introduction 23 LAN Command register 23 manchester management register 29 missed packet error counter register 29 multicast filter table registers 27 offset addressing 23 page select 24 receive boundary page register 23 receive buffer end register 32 receive buffer starting address register 30 receive buffer table pointer registers 34 receive burst starting address registers 30 receive byte count registers 31 receive configuration register 31 receive packet status register 33 receive start page register 33 receive stop page register 34 received byte count register 26 station address registers 34 transfer buffer end register 37 - 38 transfer count registers 37 transmit buffer pointer registers 39 transmit buffer starting address register 36 transmit burst starting address registers 35 transmit configuration register 36 transmit frame length registers 36 transmit start page registers 38 transmit status register 38 LED test and enable fields 29 LEDs 76 Link integrity test field 21, 75 Link integrity test function 21, 75 Link status LED readback field 29 Linked-list buffering introduction 23 selecting 26 Linked-list buffering format 88 Linked-list receiver buffering 88 LIT 22, 75 LLED 7, 75 Loopback mode 69 LPOE 7 120 83C795 M M16CS 7, 51 M16EN 17 M16EN bit 45 MA lines 7 MAC protocol type select field 16 MAC receiver address recognition logic 71 basic functions 70 CRC checking 71 interface to manchester decoder 70 loopback paths 70 receive deserialization 70 receive protocol FSM 72 received byte counter and early receive warning 71 receiver blinding 73 reception process 72 MAC-to-PHY interface 74 Manchester decoder 69 Manchester enable/disable field 29 Manchester encoder 74 Manchester encoder/decoder enabling and controlling 29 Manchester management register 29, 74 Mask interrupt sources field 17 Memory 16-bit enable field 17 Memory address generation 48 Memory bit width select 7 Memory bus structure 51 Memory bus width control 51 Memory cache 44 advantages 44 read mode 44 staggered address transfers 45 using Micro-channel adapters 46 zero wait state response to host 45 Memory enable field 14 MEMR 7 MEMW 7 Missed packet counter register 72 Missed packet error counter register 29 Missed packet field 33 Modifying the transmit queue 82 Monitor mode 33 Multicast field table registers 27 Multicast frames receiving 32 Multiple packet transmissions 80 Multiple packet transmit mode 28 N Non-802.3 protocols 79 Non-8390 features enabling 26 Non-deferred field 39 - 40 Normal map buffering See ring-style buffering O Operating conditions 90 Operation on Micro-Channel adapters 46 Oscillator 74 OSR 7 Out-of-window collision field 38, 78 Overwrite warning enable field 27 Overwrite warning field 28 Ownership of buffers 82 P Package description 116 Package dimensions 116 - 117 Packet received enable field 28 Packet received field 28 Packet received intact field 33 Packet transmitted enable field 28 Packet transmitted field 28, 39 - 40 Page select field 24 PC-98 bus support 50 PHY-to-MAC interface 68 Pin list 5 - 11 PLED 69 PLI 1 Plug and play 57 auto-configuration ports 57 boot bit 20 buffer memory limitations 64 configuration and activation 59 configuration registers 59 configuring as a boot card 64 configuring with an I/O-mapped pipe 64 enable bit 22 isolation 59 plug and play jumper installed bit 16 PnP and I/O mapped pipe bit 19 resource string 62 states 58 PNJMP 16 PNPBOOT 20, 64 PNPEN 22 PNPIOP 19, 64 POS ID registers 19 121 83C795 Preamble generator 76 Promiscuous mode 71 Promiscuous reception field 31 Pulse train sourcing 64 R RAM address register 20 RAM base address field 20 RAM offset field 14 RAMCS1 8 RAMOE 7 RAMWR 7 Recall EEROM field 15 Receieve boundary page register 23 Receive abort frame field 31 Receive broadcast frames field 32 Receive buffer end register 32, 88 Receive buffer starting address register 30 Receive buffer table pointer registers 34, 89 Receive burst starting address registers 30 Receive byte count registers 31 Receive configuration register 31, 71, 73 Receive error enable field 28 Receive error field 28 Receive LED readback 29 Receive multicast frames 32 Receive packet buffering 83 Receive packet status register 33 Receive runt frames field 32 Receive start page register 33, 88 Receive stop page register 34 Received byte count register 26 Received byte counter 71 Receiver blinding 73 Receiver disable field 33 Receiver fields 72 CRC field 73 DA field 73 end-of-frame 73 SA and data fields 73 SFD field 73 Receiver network interface 68 Receiver protocol FSM 72 Recommended operating conditions 90 Register overview 12 Relocating RAM and ROM base addresses in tandem 48 RESET 7, 53 Reset network interface controller field 14 Reset status field 28 Resource string 62 Restart field 16 Retrieval and storage of host configuration registers 54 Revision number indication field 18 Ring arrangements 86 Ring of buffers 83 Ring-buffering selecting 26, 79 Ring-style buffering introduction 23 RLED 8 ROM base address field 21 ROM control register 20 ROM offset field 17 ROM size selection 48 ROM window size field 20 Runt frames receiving 32 Runts frames receiving 71 RX+/RX- 8 S SA address lines 8 Save error packets field 32 SBHE 8, 51 SD data lines 8 Sending multiple transmissions 80 Single packet transmission 80 Slot timer 77 Smart squelch digital noise filter 69 SMEMR 8 SMEMW 8 Software interrupt field 17 SQE test 75 Squelch circuitry 69 Staggered address transfers 45 Start bit field 24, 72 Start page 38 Start page register 33 Start-of-frame delimiter (SFD) 70, 73 Station address registers 34 Status indicators 75 Stop backup modifications 26 Stop bit field 24, 72 Stop page register 34 Store to non-volatile field 15 Supporting non-802.3 protocols 79 Switch register bit 14 Switch register set 16 122 83C795 T Timers backoff timer 77 collision counter 77 heartbeat detection 77 slot timer 77 truncated binary exponential backoff algorithm 77 Timing diagrams 93 - 115 parameters 94 TLED 9 TPR+/TPR- 9 TPRX polarity LED readback field 29 TPX+/TPX- 9 TPX1/TPX2 74 TPX2+/TPX2- 9 Transfer buffer end register 37 - 38, 80 Transfer count registers 37 Transmission initialization 77 Transmission process 77 Transmit buffer pointer registers 39, 80 Transmit buffer starting address register 36, 80 Transmit burst starting address registers 35 Transmit configuration register 36, 76 Transmit error enable field 28 Transmit error field 28, 78 Transmit frame length registers 36, 80 Transmit LED readback 29 Transmit packet initiation field 24 Transmit packets buffer ownership 82 multiple packet transmissions 80 single packet transmission 80 transmit queue modification 82 Transmit protocol FSM 76 Transmit queue modifying 82 Transmit serializer 76 Transmit start page registers 38 Transmit status register 38, 78, 80, 82 Transmit underrun 78 Transmitted with collisions field 39 - 40 Transmitter basic function 76 collisions 78 CRC generator 76 early transmit underrun protection 78 extensions beyond 802.3 79 FIFO 77 initialization 77 operation 77 preamble generator 76 timers 77 transmission process 77 transmit protocol FSM 76 transmit serializer 76 transmit underrun 78 Transmitter network interface 74 Transmitter operation 77 Twisted-pair differential driver transmitter 74 Twisted-pair differential receiver 69 TX+/TX- 9, 74 TXD 76 U Unlock EEROM storage field 15 Using an external EEROM 54 V VDD pins 9 VSS pins 9 W Wait state selection 26 WaitForKey 58 WRAPEN 87 X X1/X2 9, 74 XTXD 76 Z Zero wait state enable field 21 Zero wait state in 16-bit transfers 52 Zero wait state response to the host 50 ZWS 9, 50 - 51 response to host 45 123 |
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